@article{Ghoreishizadeh:2017:10.1109/TCSI.2017.2731659,
author = {Ghoreishizadeh, S and Haci, D and Liu, Y and Donaldson, N and Constandinou, TG},
doi = {10.1109/TCSI.2017.2731659},
journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
pages = {3056--3067},
title = {Four-Wire Interface ASIC for a Multi-Implant Link},
url = {http://dx.doi.org/10.1109/TCSI.2017.2731659},
volume = {64},
year = {2017}
}

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TY  - JOUR
AB  - This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical ‘optrodes’ that facilitate a bidirectional neural interface (electrical recording, optical stimulation), and chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate(up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) which is superimposed on a power carrier. On-chip power management provides an unregulated 5V DC supply with up to 2.5mA output current for stimulation, and two regulated voltages (3.3V and 3V) with 60 dB PSRR for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35 um CMOS technology, occupying 1.5mm2 silicon area,and consumes a quiescent current of 91.2u A. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.
AU  - Ghoreishizadeh,S
AU  - Haci,D
AU  - Liu,Y
AU  - Donaldson,N
AU  - Constandinou,TG
DO  - 10.1109/TCSI.2017.2731659
EP  - 3067
PY  - 2017///
SN  - 1549-8328
SP  - 3056
TI  - Four-Wire Interface ASIC for a Multi-Implant Link
T2  - IEEE Transactions on Circuits and Systems I: Regular Papers
UR  - http://dx.doi.org/10.1109/TCSI.2017.2731659
UR  - http://ieeexplore.ieee.org/document/8010903/
VL  - 64
ER  - 

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