Citation

BibTex format

@article{Liu:2017:10.1109/TBCAS.2017.2759339,
author = {Liu, Y and Luan, S and Williams, I and Rapeaux, A and Constandinou, TG},
doi = {10.1109/TBCAS.2017.2759339},
journal = {IEEE Transactions on Biomedical Circuits and Systems},
title = {A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput},
url = {http://dx.doi.org/10.1109/TBCAS.2017.2759339},
year = {2017}
}

RIS format (EndNote, RefMan)

TY  - JOUR
AB - Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.
AU - Liu,Y
AU - Luan,S
AU - Williams,I
AU - Rapeaux,A
AU - Constandinou,TG
DO - 10.1109/TBCAS.2017.2759339
PY - 2017///
SN - 1932-4545
TI - A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput
T2 - IEEE Transactions on Biomedical Circuits and Systems
UR - http://dx.doi.org/10.1109/TBCAS.2017.2759339
UR - http://hdl.handle.net/10044/1/51243
ER -