CAP Research Roulette
PhD students and Postdocs of the Control and Power Group present their research projects
Every week, one speaker (selected randomly two weeks in advance) will give a 15min talk followed by a 10min discussion. The talks might be conference contributions, initial research ideas of talks for the Late Stage Review or Early Stage Assessment.
After the talk, the participants will have coffee and cake/biscuits together in Faraday Cage. This provides an excellent opportunity to get in touch with the participants and have a follow-up discussion with the speaker. Everyone is invited, with interest in the following topics spanning control and power:
- control theory and applications
- power electronics
- power systems and energy
- smart grids
Currently, the audience consists of MSc students, PhD students and Postdocs of the Control and Power group.
This week's talk
Speaker: Caspar Collins
When: Wed 12/12/2018 14:00-14:30
Where: Room EEE 1109B
Title: Comparative Analysis of an MV Neutral Point Clamped AC-CHB Converter with DC Fault Ride-through Capability
Abstract: The AC side cascaded H-bridge converter with a two-level main bridge has previously been proposed as a fault tolerant converter for HVDC. This paper explores the benefits of replacing the two-level bridge with a neutral point clamped three-level (NPC) bridge for MVDC applications and defines the optimum operating conditions for this case. By modifying the topology to include an NPC main bridge, the peak stack voltage during normal operation is decreased considerably which results in a 58% reduction in the required number of sub-modules (SM), thereby significantly increasing efficiency. However, this sacrifices the fault ride-through capability as the stacks are no longer able to support the AC voltage and thus two new SM topologies are proposed. The proposed topologies function as single full-bridges with two capacitors in parallel during normal operation. Under fault conditions, the SMs divide into two series connected full-bridges to enable DC fault ride-through. Reverse-blocking IGCTs or ultra-fast mechanical switches are used to bypass the IGBTs which are unused in normal operation and therefore the topology maintains a high efficiency. Simulation results are shown, and the proposed topologies are compared with more conventional designs in terms of efficiency, energy storage requirement and device count.
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