Imperial College London
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Alexander Tapper

Faculty of Natural Sciences, Department of Physics

Professor of Physics
 
 
 
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Contact

 

+44 (0)20 7594 1551a.tapper Website

 
 
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Location

 

508Blackett LaboratorySouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Aggleton:2017:10.23919/FPL.2017.8056825,
author = {Aggleton, R and Ardila-Perez, L and Ball, FA and Balzer, MN and Brooke, J and Calligaris, L and Caselle, M and Cieri, D and Clement, EJ and Hall, G and Harder, K and Hobson, PR and Iles, GM and James, T and Manolopoulos, K and Matsushita, T and Morton, AD and Newbold, D and Paramesvaran, S and Pesaresi, M and Reid, ID and Rose, AW and Sander, O and Schuh, T and Shepherd-Themistocleous, C and Shtipliyski, A and Summers, SP and Tapper, A and Tomalin, I and Uchida, K and Vichoudis, P and Weber, M},
doi = {10.23919/FPL.2017.8056825},
publisher = {IEEE},
title = {A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN},
url = {http://dx.doi.org/10.23919/FPL.2017.8056825},
year = {2017}
}
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RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - The Compact Muon Solenoid (CMS) experiment at CERN is scheduled for a major upgrade in the next decade in order to meet the demands of the new High Luminosity Large Hadron Collider. Amongst others, a new tracking system is under development including an outer tracker capable of rejecting low transverse momentum particles by looking at the coincidences of hits (stubs) in two closely spaced sensor layers in the same tracker module. Accepted stubs are transmitted off-detector for further processing at 40 MHz. In order to maintain under the increased luminosity the Level-1 trigger rate at 750 kHz, tracker data need to be included in the decision making process. For this purpose, a system architecture has to be developed that will be able to identify particles with transverse momentum above 3 GeV/c by building tracks out of stubs, while achieving an overall processing latency of maximum 4us. Targeting these requirements the current paper presents an FPGA-based track finding architecture that identifies track candidates in real-time and bases its functionality on a fully time-multiplexed approach. As a proof of concept, a hardware system has been assembled targeting the MP7 MicroTCA processing card that features a Xilinx Virtex-7 FPGA, demonstrating a realistic slice of the track finder. The paper discusses the algorithms' implementation and the efficient utilisation of the available FPGA resources, it outlines the system architecture, and presents some of the hardware demonstrator results.
AU  - Aggleton,R
AU  - Ardila-Perez,L
AU  - Ball,FA
AU  - Balzer,MN
AU  - Brooke,J
AU  - Calligaris,L
AU  - Caselle,M
AU  - Cieri,D
AU  - Clement,EJ
AU  - Hall,G
AU  - Harder,K
AU  - Hobson,PR
AU  - Iles,GM
AU  - James,T
AU  - Manolopoulos,K
AU  - Matsushita,T
AU  - Morton,AD
AU  - Newbold,D
AU  - Paramesvaran,S
AU  - Pesaresi,M
AU  - Reid,ID
AU  - Rose,AW
AU  - Sander,O
AU  - Schuh,T
AU  - Shepherd-Themistocleous,C
AU  - Shtipliyski,A
AU  - Summers,SP
AU  - Tapper,A
AU  - Tomalin,I
AU  - Uchida,K
AU  - Vichoudis,P
AU  - Weber,M
DO  - 10.23919/FPL.2017.8056825
PB  - IEEE
PY  - 2017///
TI  - A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN
UR  - http://dx.doi.org/10.23919/FPL.2017.8056825
UR  - http://hdl.handle.net/10044/1/55089
ER  -
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