Publications
150 results found
Zylinski M, Nassibi A, Rakhmatulin I, et al., 2024, Deployment of Artificial Intelligence Models on Edge Devices: A Tutorial Brief, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol: 71, Pages: 1738-1743, ISSN: 1549-7747
Artificial intelligence (AI) on an edge device has enormous potential, including advanced signal filtering, event detection, optimization in communications and data compression, improving device performance, advanced on-chip process control, and enhancing energy efficiency. In this tutorial, we provide a brief overview of AI deployment on edge devices, and describe the process of building and deploying a neural network model on a digital edge device. The primary challenge when deploying an AI model in circuits is to fit the model within the constraints of the limited resources as the restricted memory capacity on IoT circuits and the finite computational power impose constraints on the utilization of deep neural networks on IoT. We address this issue by elucidating methods for optimizing neural network models. Part of the tutorial also covers the deployment of deep neural network on logic circuits, as significantly enhanced computational speed can be attained by transitioning the AI paradigm from neural networks to learning automata algorithms. This shift involves a move from arithmetic-based calculations to logic-based approaches. This transformation facilitates the deployment of AI onto Field-Programmable Gate Arrays (FPGAs). The last part of the tutorial covers the emerging topic of in-memory computation of the multiply-accumulate operation. Transferring computations to analog memories has the potential to improve speed and energy efficiency compared to digital architectures, potentially achieving improvements of several orders of magnitude. It is our hope that this tutorial will assist researchers and engineers to integrate AI models on edge devices, facilitating rapid and reliable implementation.
Alshaya A, Pamarti S, Papavassiliou C, 2024, FPGA crystal oscillator circuit emulation based on wave digital filter, IEEE Transactions on Very Large Scale Integration Systems, Vol: 32, Pages: 103-115, ISSN: 1063-8210
The design cycle of analog and mixed signal components requires the designer to iteratively perform analogsimulations, layout, fabrication, and hardware testing. Unlike digital designs, system verification is a difficult task in analog designs, primarily due to a lack of emulation. Thus, a method to emulate analog and mixed signal components on digital hardware would be highly beneficial. In this work, a high-quality factor crystal oscillator circuit is implemented on a Xilinx Vertex 7 FPGA using the Wave Digital Filter based model with a non-linear lookup table for modeling transistor characteristics. The number of required hardware resources was minimized while ensuring that the accuracy of the emulation shows an almost perfect match with the SPICE simulations. The wave digital filter model was designed with a tree structure so that it only requires 32 clockcycles to compute a complete sample. The resulting emulation computes a sample at 18.75 MHz while running on an FPGA with a 600 MHz clock.
Alshaya A, Malik A, Mifsud A, et al., 2023, Comparison of 1T1R and 1C1R ReRAM arrays, 2023 6th International Conference on Circuits, Systems and Simulation (ICCSS 2023), Publisher: IOP Publishing, Pages: 1-8, ISSN: 1742-6588
The rise of memristors with potential applications in memory has attracted wide interests. Memristors are typically assembled in crossbar arrays with data bits encoded by the resistance of individual cells. The 1T1R cell structure is the most popular for memristive memory as it eliminates sneak path currents. The transistor not only allows for flexible selection of memory cells but also facilitates the programming for computing-in-memory applications. In this paper, we replace the selector in the 1T1R configuration with a capacitor to form a selectorless and passive combination of ReRAM structure. Moreover, we evaluate the merits of the two structures in SkyWater 130nm CMOS technology by comparing the writing technique, power consumption, switching speed, and memory density. Furthermore, we compared the complexity of the readout method between 1T1R and 1C1R for a memory application. This work shows that the 1C1R configuration is a promising memory structure that consumes less energy, switches faster, has higher density, and has a simpler readout method when compared to 1T1R.
Pucci N, Papavassiliou C, Mitcheson PD, 2023, Synchronous operation of high frequency inductive power transfer systems through injection locking, IEEE Transactions on Power Electronics, Vol: 38, Pages: 11984-11994, ISSN: 0885-8993
High frequency inductive power transfer systems can be designed for operation with high tolerance to misalignment and large air-gaps, making it possible to operate in highly dynamic environments. Most examples in the literature use a single active transmitter and a single passive receiver (active-passive approach). Such systems are limited to unidirectional power flow and are susceptible to detuning of the transmitter due to changes of reflected reactance stemming from diode non-linearities. This also limits the range of coupling over which the system can be operated efficiently. Therefore there is significant potential for expanding the range of applications of inductive power transfer systems by moving to an active-active configuration. This will enable bidirectional power flow, power routing through several nodes and on-the-fly retuning to eliminate reflected reactances. One of the greatest challenges in achieving an active secondary in an IPT system is obtaining a stable frequency and phase reference for the synchronous rectifier/transceiver with respect to the transmitter coil current and hence magnetic field. Various methods for synchronisation have been proposed in the literature, but they either require a separate, out of band communication link, or are difficult to scale to MHz operation. This paper describes an alternative to the existing solutions, using an injection locked oscillator to provide optimal phase tracking. A series of candidate feedback configurations are also proposed to provide high system resilience. In this work the basic principles of injection locking are described as applied to synchronous IPT transceivers and experimental results are presented demonstrating its application to a bidirectional back-to-back Class-EF configuration operating at 13.56 MHz, with coupling factors ranging from 1.9 % to 8.4 % and power levels of up to 25 W.
Si Z, Wang C, Jiang X, et al., 2023, Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 70, Pages: 3497-3508, ISSN: 1549-8328
Prodromakis T, Papavassiliou C, Si Z, et al., 2023, An improved data-driven memristor model accounting for sequences stimulus features, 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, ISSN: 2158-1525
The natural similarity between the emerging memristive technology and synapses makes memristor a promising device in the spiking input based neuromorphic systems. However, while asynchronous signal processing relies on memristor's response under the pulses stimulus, hardly any memristor models take the impact of sequences features on device behaviour into account. This paper proposes an optimized data-driven compact memristor model where the boundary of its internal state variable-resistive state (RS) is modelled with pulse amplitude and pulse width based on characterisation data. The model has been developed in Verilog-A and verified in Cadence Virtuoso Electronic Design Automation (EDA) tools. Based on the simulation, we further introduce a new concept “Effective Time Window”. Along with the observed pulse width modulated resistance, more potential circuit applications can be implemented based on a more realistic memristor switching behaviour.
Malik A, Mifsud A, Alshaya A, et al., 2023, The design of a resistive switching characterisation platform based on discrete current-conveyors, 2023 12th International Conference on Modern Circuits and Systems Technologies (MOCAST), Publisher: IEEE, Pages: 1-4
In this paper we propose a current-conveyor based circuit to characterise resistive switching devices. The circuit relies on open-loop current-mode techniques that are in principle faster than existing solutions that rely on transimpedance amplifiers for biasing and current sensing [1]. The circuit is able to apply a voltage across a test device and simultaneously provide a measure of current flowing through it. The circuit therefore, results in a compact solution that can be scaled-up to characterise crossbar devices in parallel. In this paper we describe, simulate and evaluate a discrete version of the proposed circuit. We also verify a PCB implementation that is capable of forming, writing and reading different types of resistive switching devices.
Raeis-Hosseini N, Georgiadou DG, Papavassiliou C, 2023, Addition to “High on/off ratio carbon quantum dot–chitosan biomemristors with coplanar nanogap electrodes”, ACS Applied Electronic Materials, Vol: 5, Pages: 1313-1313, ISSN: 2637-6113
Raeis-Hosseini N, Georgiadou DG, Papavassiliou C, 2023, High on/off ratio carbon quantum dot–chitosan biomemristors with coplanar nanogap electrodes, ACS Applied Electronic Materials, Vol: 5, Pages: 138-145, ISSN: 2637-6113
A carbon-based natural nanocomposite material comprising carbon quantum dots (CQDs) is dispersed in a chitosan matrix. The CQD–chitosan nanocomposite serves as a solid polymer electrolyte layer of a biomemristor with a Au/CQD–chitosan/Al structure. The active layer of the CQD–chitosan nanocomposite is deposited from its solution on top of coplanar asymmetric nanogap (∼15 nm) Al–Au electrodes, patterned via adhesion lithography. The CQD–chitosan biomemristor presents a high on/off ratio (>106) and reproducible and reliable bipolar resistive switching behavior. An endurance of 160 cycles was recorded, while the high and low resistance states remained stable for more than 104 s. This study highlights the potential of both the CQD–chitosan material and nanogap electrode structures for application in nanoscale biocompatible memory devices.
Malik A, Papavassiliou C, 2023, A Memristive True Random Number Generator
In this work we propose a method to generate true random numbers which exploits the large variation of the transient behaviour of the memristor's resistive state, when programmed by very short pulses. Analog signal processing techniques are used to overcome drift-related limitations to the spectral purity and the run length of memristive random number generators. The resulting random bit sequences pass NIST randomness tests.
Alshaya A, Malik A, Mifsud A, et al., 2023, Experimental Results of 1C1R Structure Based on Knowm Memristor
This paper presents experimental findings of a new passive memristive memory structure called ICIR, which involves the series connection of one capacitor and one ReRAM. The ICIR configuration, illustrated in Fig. 1, shows great potential as a memory structure due to its high density, reduced power consumption, improved switching speed, and, notably, the monotonic relationship between the charges on the capacitor and the memristance. In this paper, we have implemented a ICIR structure utilizing a discrete Knowm memristor with Self-Directed Channel (SDC) Memristor material stack. Our experiment involved performing forming, writing, and reading operations. The forming and writing operation were done by applying pulses with a width lower than 15 Rmem C. This approach was adopted considering the high-pass filter characteristics inherent in the ICIR configuration. The results demonstrate that the ICIR structure effectively stores 1-bit of information by dividing the memristor's resistance (memristance) into two states: 15.17 KΩ (bit 1) and 282K Ω (bit 0). The memristance reading operation in this experiment was based on measuring the time required for the capacitor to charge (τ=Rmem C).
Alshaya A, Malik A, Mifsud A, et al., 2023, A Fully Passive Selectorless ReRAM Array, Pages: 341-345, ISSN: 1548-3746
The memristor is a revolutionary passive device that has gained popularity in recent years as a possible contender for next-generation nonvolatile memory and analogue computing. This work presents a passive selectorless memristive memory crossbar array. It presents a 16x16 array with a one capacitor and one memristor (1CIR) core cell. The 1CIR configuration is a promising memory structure because of its high density, lower power consumption, faster speed, and more importantly the monotonic relationship between the charges on the capacitor and the memristance. Data readout in this work is carried out by an 8-bit time to digital converter. Results show that the 1C1R structure can successfully store 1-bit of information by splitting the resistance of the memristor (memristance) into two states of 10.07KΩ (bit 1) and 3.38 MΩ (bit 0). The total area of the proposed array is 0.4 mm2 in a SkyWater130nm CMOS technology.
Jiang X, Sbandati C, Reynolds G, et al., 2023, A Neural Recording System with 16 Reconfigurable Front-end Channels and Memristive Processing/Memory Unit, 21st IEEE Interregional NEWCAS Conference (NEWCAS), Publisher: IEEE, ISSN: 2472-467X
Huang G, Wang C, Si Z, et al., 2023, An Improved Data-Driven Memristor Model Accounting for Sequences Stimulus Features, 56th IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, ISSN: 0271-4302
Alshaya A, Han Q, Papavassiliou C, 2022, Passive selectorless memristive structure with one capacitor-one memristor, 2022 International Conference on Microelectronics (ICM), Publisher: IEEE, Pages: 121-124
Memristor memory has garnered more interest as a potential future non-volatile memory. One access transistor and one memristor (1T1R) cell structure can be utilized to eliminate the issue of sneak path current in crossbar-structured memristor memories. However, it has lower switching speed and high-power consumption. In this paper, a novel passive selectorless structure cell has been studied. One capacitor-One Memristor (1C1R) structure is proposed as a passive access device that can be controlled by the applied signal width. The 1C1R successfully writes and reads 1-bit information with two resistance value: 3.38MΩ as bit 0, and 10.07KΩ as a bit 1. 1C1R topology is proposed as a promising structure that has lower power consumption and faster switching speed compared to 1T1R. In addition, this work addresses the readout technique with 1C1R structure. The RRAM is implemented by SkyWater Verilog-A model.
Alshaya A, Han Q, Papavassiliou C, 2022, RRAM, device, model and memory, 2022 International Conference on Microelectronics (ICM), Publisher: IEEE, Pages: 117-120
The memristor is an innovative passive electrical device that has gained popularity in recent years as a potential candidate for next-generation non-volatile memory (NVM) and analog computing. This popularity stems from the memristor’s ability to store information in a manner that is inaccessible to external power sources. It is possible to electrically modify the resistance state, and this change will be retained even after the external bias has been removed. This is a distinctive electrical characteristic of the device. In this paper, we present a comprehensive presentation and illustration about SkyWater memristor device and model. A read/write operation for a standalone memristor (1R), and a 1 transistor 1 memristor (1T1R) were conducted. The RRAM successfully can be written and read 1-bit information by dividing the resistance of the memristor (memristance) into two states of RON=10.07 KΩ as a bit 1 and ROFF=3.38 MΩ as a bit 0.
Wang C, Si Z, Jiang X, et al., 2022, Multi-State Memristors and Their Applications: An Overview, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol: 12, Pages: 723-734, ISSN: 2156-3357
Mifsud A, Shen J, Feng P, et al., 2022, A CMOS-based characterisation platform for emerging RRAM technologies, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 75-79
Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1kΩ and 10MΩ with a minimum voltage range of ±1.5V on the device.
Xie L, Shen J, Mifsud A, et al., 2022, A wide dynamic range read-out system for resistive switching technology, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2003-2007
The memristor, because of its controllability over a wide dynamic range of resistance, has emerged as a promising device for data storage and analog computation. A major challenge is the accurate measurement of memristance over a wide dynamic range. In this paper, a novel read-out circuit with feedback adjustment is proposed to measure and digitise input current in the range between 20nA and 2mA. The magnitude of the input currents is estimated by a 5-stage logarithmic current-to-voltage amplifier which scales a linear analog-to-digital converter. This way the least significant bit tracks the absolute input magnitude. This circuit is applicable to reading single memristor conductance, and is also preferable in analog computing where read-out accuracy is particularly critical. The circuits have been realized in Bipolar-CMOS-DMOS (BCD) Gen2 technology.
Shen J, Mifsud A, Xie L, et al., 2022, A high-voltage characterisation platform for emerging resistive switching technologies, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 3537-3541
Emerging memristor-based array architectures have been effectively employed in non-volatile memories and neuro-morphic computing systems due to their density, scalability and capability of storing information. Nonetheless, to demonstrate a practical on-chip memristor-based system, it is essential to have the ability to apply large programming voltage ranges during the characterisation procedures for various memristor technologies. This work presents a 16x16 high voltage memristor characterisation array employing high voltage CMOS circuitry. The proposed system has a maximum programming range of ±22V to allow on-chip electroforming and I-V sweep. In addition, a Kelvin voltage sensing system is implemented to improve the readout accuracy for low memristance measurements. This work addresses the limitation of conventional CMOS-memristor platforms which can only operate at low voltages, thus limiting the characterisation range and integration options of memristor technologies.
Nassibi A, Papavassiliou C, Atashzar SF, 2022, Depression diagnosis using machine intelligence based on spatiospectrotemporal analysis of multi-channel EEG, MEDICAL & BIOLOGICAL ENGINEERING & COMPUTING, Vol: 60, Pages: 3187-3202, ISSN: 0140-0118
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Maheshwari S, Serb A, Papavassiliou C, et al., 2022, An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 69, Pages: 3512-3525, ISSN: 1549-8328
Foster P, Huang J, Serb A, et al., 2022, An FPGA-based system for generalised electron devices testing, Scientific Reports, Vol: 12, ISSN: 2045-2322
Electronic systems are becoming more and more ubiquitous as our world digitises. Simultaneously, even basic components are experiencing a wave of improvements with new transistors, memristors, voltage/current references, data converters, etc, being designed every year by hundreds of R &D groups world-wide. To date, the workhorse for testing all these designs has been a suite of lab instruments including oscilloscopes and signal generators, to mention the most popular. However, as components become more complex and pin numbers soar, the need for more parallel and versatile testing tools also becomes more pressing. In this work, we describe and benchmark an FPGA system developed that addresses this need. This general purpose testing system features a 64-channel source-meter unit, and [Formula: see text] banks of 32 digital pins for digital I/O. We demonstrate that this bench-top system can obtain [Formula: see text] current noise floor, [Formula: see text] pulse delivery at [Formula: see text] and [Formula: see text] maximum current drive/channel. We then showcase the instrument's use in performing a selection of three characteristic measurement tasks: (a) current-voltage characterisation of a diode and a transistor, (b) fully parallel read-out of a memristor crossbar array and (c) an integral non-linearity test on a DAC. This work introduces a down-scaled electronics laboratory packaged in a single instrument which provides a shift towards more affordable, reliable, compact and multi-functional instrumentation for emerging electronic technologies.
Raeis-Hosseini N, Chen S, Papavassiliou C, et al., 2022, Impact of Zr top electrode on tantalum oxide-based electrochemical metallization resistive switching memory: towards synaptic functionalities, RSC Advances: an international journal to further the chemical sciences, Vol: 12, Pages: 14235-14245, ISSN: 2046-2069
Electrochemical metallization memory (ECM) devices have been made by sub-stoichiometric deposition of a tantalum oxide switching film (Ta2O5−x) using sputtering. We investigated the influence of zirconium as the active top electrode material in the lithographically fabricated ECM devices. A simple capacitor like (Pt/Zr/Ta2O5−x/Pt) structure represented the resistive switching memory. A cyclic voltammetry measurement demonstrated the electrochemical process of the memory device. The I–V characteristics of ECMs show stable bipolar resistive switching properties with reliable endurance and retention. The resistive switching mechanism results from the formation and rupture of a conductive filament characteristic of ECM. Our results suggest that Zr can be considered a potential active electrode in the ECMs for the next generation of nonvolatile nanoelectronics. We successfully showed that the ECM device can work under AC pulses to emulate the essential characteristics of an artificial synapse by further improvements.
Malik A, Papavassiliou C, Stathopoulos S, 2022, An Absorbing Markov Chain Model for Stochastic Memristive Devices, 11th International Conference on Modern Circuits and Systems Technologies (MOCAST), Publisher: IEEE
Si Z, Wang C, Malik A, et al., 2022, Memristor-assisted Background Calibration for Analog-to-Digital Converter, 20th IEEE Interregional NEWCAS Conference (IEEE NEWCAS), Publisher: IEEE, Pages: 470-474
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Wang D, Wang S, Prodromakis T, et al., 2022, Delta-Sigma Modulator Design Using a Memristive FIR DAC, 29th IEEE International Conference on Electronics, Circuits and Systems (IEEE ICECS), Publisher: IEEE
Alshaya A, Komies S, Xie L, et al., 2022, Analogue Circuits Real-Time Emulation based on Wave Digital Filter, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1566-1569, ISSN: 0271-4302
Maheshwari S, Stathopoulos S, Wang J, et al., 2021, Design flow for hybrid CMOS/memristor systems--Part II: circuit schematics and layout, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4876-4888, ISSN: 1549-8328
\normalsize The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.
Maheshwari S, Stathopoulos S, Wang J, et al., 2021, Design flow for hybrid CMOS/memristor systems--Part I: modeling and verification steps, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4862-4875, ISSN: 1549-8328
Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.
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