Imperial College London

Dr Christos Papavassiliou

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Reader in Instrumentation Electronics
 
 
 
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Contact

 

+44 (0)20 7594 6325c.papavas Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

915Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Chen:2013:10.1109/UKSim.2013.86,
author = {Chen, W and Papavassiliou, C},
doi = {10.1109/UKSim.2013.86},
pages = {774--779},
publisher = {IEEE},
title = {A Low Power 10-bit Time-to-Digital Converter Utilizing Vernier Delay Lines},
url = {http://dx.doi.org/10.1109/UKSim.2013.86},
year = {2013}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AU - Chen,W
AU - Papavassiliou,C
DO - 10.1109/UKSim.2013.86
EP - 779
PB - IEEE
PY - 2013///
SP - 774
TI - A Low Power 10-bit Time-to-Digital Converter Utilizing Vernier Delay Lines
UR - http://dx.doi.org/10.1109/UKSim.2013.86
UR - http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=000325091800137&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202
ER -