Imperial College London

DrChristos-SavvasBouganis

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Senior Lecturer
 
 
 
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Contact

 

+44 (0)20 7594 6144christos-savvas.bouganis Website

 
 
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Location

 

904Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
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117 results found

De Souza Rosa L, Bouganis C, Bonato V, 2018, Scaling up modulo scheduling for high-level synthesis., Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN: 0278-0070

High-Level Synthesis tools have been increasingly used within the hardware design community to bridge the gap between productivity and the need to design large and complex systems. When targeting heterogeneous systems, where the CPU and the FPGA fabric are both available to perform computations, a design space exploration is usually carried out for deciding which parts of the initial code should be mapped to the FPGA fabric such as the overall system’s performance is enhanced by accelerating its computation via dedicated processors. As the targeted systems become more complex and larger, leading to a large design space exploration, the fast estimative of the possible acceleration that can be obtained by mapping certain functionality into the FPGA fabric is of paramount importance. Loop pipelining, which is responsible for the majority of HLS compilation time, is a key optimization towards achieving high-performance acceleration kernels. A new modulo scheduling algorithm is proposed, which reformulates the classical modulo scheduling problem and leads to a reduced number of integer linear problems solved, resulting in large computational savings. Moreover, the proposed approach has a controlled trade-off between solution quality and computation time. Results show the scalability is improved efficiently from quadratic, for the state-of-the-art method, to linear, for the proposed approach, while the optimized loop suffers a 1% (geomean) increment in the total number of cycles.

JOURNAL ARTICLE

Kouris A, Venieris SI, Bouganis C-S, 2018, CascadeCNN: Pushing the performance limits of quantisation.

CONFERENCE PAPER

Kyrkou C, Plastiras G, Theocharides T, Venieris SI, Bouganis C-Set al., 2018, DroNet: Efficient Convolutional Neural Network Detector for Real-Time UAV Applications, Design, Automation and Test in Europe Conference and Exhibition (DATE), Publisher: IEEE, Pages: 967-972, ISSN: 1530-1591

CONFERENCE PAPER

Rizakis M, Venieris SI, Kouris A, Bouganis C-Set al., 2018, Approximate FPGA-based LSTMs under Computation Time Constraints.

CONFERENCE PAPER

Rizakis M, Venieris SI, Kouris A, Bouganis C-Set al., 2018, Approximate FPGA-Based LSTMs Under Computation Time Constraints., Publisher: Springer, Pages: 3-15

CONFERENCE PAPER

Shafique M, Theocharides T, Bouganis C-S, Hanif MA, Khalid F, Hafiz R, Rehman Set al., 2018, An overview of next-generation architectures for machine learning: Roadmap, opportunities and challenges in the IoT era., Publisher: IEEE, Pages: 827-832

CONFERENCE PAPER

Vasileiadis M, Malassiotis S, Giakoumis D, Bouganis C-S, Tzovaras Det al., 2018, Robust Human Pose Tracking For Realistic Service Robot Applications, 16th IEEE International Conference on Computer Vision (ICCV), Publisher: IEEE, Pages: 1363-1372, ISSN: 2473-9936

Robust human pose estimation and tracking plays an integral role in assistive service robot applications, as it provides information regarding the body pose and motion of the user in a scene. Even though current solutions provide high-accuracy results in controlled environments, they fail to successfully deal with problems encountered under real-life situations such as tracking initialization and failure, body part intersection, large object handling and partial-view body-part tracking. This paper presents a framework tailored for deployment under real-life situations addressing the above limitations. The framework is based on the articulated 3D-SDF data representation model, and has been extended with complementary mechanisms for addressing the above challenges. Extensive evaluation on public datasets demonstrates the framework's state-of-the-art performance, while experimental results on a challenging realistic human motion dataset exhibit its robustness in real life scenarios.

CONFERENCE PAPER

Venieris SI, Bouganis C-S, 2018, fpgaConvNet: Mapping Regular and Irregular Convolutional Neural Networks on FPGAs., IEEE Trans Neural Netw Learn Syst

Since neural networks renaissance, convolutional neural networks (ConvNets) have demonstrated a state-of-the-art performance in several emerging artificial intelligence tasks. The deployment of ConvNets in real-life applications requires power-efficient designs that meet the application-level performance needs. In this context, field-programmable gate arrays (FPGAs) can provide a potential platform that can be tailored to application-specific requirements. However, with the complexity of ConvNet models increasing rapidly, the ConvNet-to-FPGA design space becomes prohibitively large. This paper presents fpgaConvNet, an end-to-end framework for the optimized mapping of ConvNets on FPGAs. The proposed framework comprises an automated design methodology based on the synchronous dataflow (SDF) paradigm and defines a set of SDF transformations in order to efficiently navigate the architectural design space. By proposing a systematic multiobjective optimization formulation, the presented framework is able to generate hardware designs that are cooptimized for the ConvNet workload, the target device, and the application's performance metric of interest. Quantitative evaluation shows that the proposed methodology yields hardware designs that improve the performance by up to 6.65$x$ over highly optimized graphics processing unit designs for the same power constraints and achieve up to 2.94$x$ higher performance density compared with the state-of-the-art FPGA-based ConvNet architectures.

JOURNAL ARTICLE

Venieris SI, Bouganis C-S, 2018, f-CNNx: A Toolflow for Mapping Multiple Convolutional Neural Networks on FPGAs.

CONFERENCE PAPER

Venieris SI, Kouris A, Bouganis C-S, 2018, Toolflows for Mapping Convolutional Neural Networks on FPGAs, ACM Computing Surveys, Vol: 51, Pages: 1-39, ISSN: 0360-0300

JOURNAL ARTICLE

Boikos K, Bouganis C-S, 2017, A high-performance system-on-chip architecture for direct tracking for SLAM., Publisher: IEEE, Pages: 1-7

CONFERENCE PAPER

Bouganis C-S, Gorgon M, Bonato V, 2017, Special issue on applied reconfigurable computing, MICROPROCESSORS AND MICROSYSTEMS, Vol: 52, Pages: 1-1, ISSN: 0141-9331

JOURNAL ARTICLE

Liu S, Bouganis C-S, 2017, Communication-Aware MCMC Method for Big Data Applications on FPGAs, 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 9-16

CONFERENCE PAPER

Liu S, Mingas G, Bouganis C-S, 2017, An Unbiased MCMC FPGA-Based Accelerator in the Land of Custom Precision Arithmetic, IEEE TRANSACTIONS ON COMPUTERS, Vol: 66, Pages: 745-758, ISSN: 0018-9340

JOURNAL ARTICLE

Mingas G, Bottolo L, Bouganis C-S, 2017, Particle MCMC algorithms and architectures for accelerating inference in state-space models, INTERNATIONAL JOURNAL OF APPROXIMATE REASONING, Vol: 83, Pages: 413-433, ISSN: 0888-613X

JOURNAL ARTICLE

Vavouras M, Duarte RP, Armato A, Bouganis C-Set al., 2017, A Hybrid ASIC/FPGA Fault-Tolerant Artificial Pancreas, International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS), Publisher: IEEE, Pages: 261-267

CONFERENCE PAPER

Venieris SI, Bouganis C-S, 2017, Latency-Driven Design for FPGA-based Convolutional Neural Networks, 27th International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488

CONFERENCE PAPER

Venieris SI, Bouganis C-S, 2017, fpgaConvNet: Automated Mapping of Convolutional Neural Networks on FPGAs (Abstract Only)., International Symposium on Field-Programmable Gate Arrays, Publisher: ACM, Pages: 291-292

CONFERENCE PAPER

Boikos K, Bouganis C-S, 2016, Semi-Dense SLAM on an FPGA SoC, 26th International Conference on Field-Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488

CONFERENCE PAPER

Duarte RP, Bouganis C-S, 2016, Variation-Aware Optimisation for Reconfigurable Cyber-Physical Systems, 7th IFIP WG 5.5/SOCOLNET Advanced Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Publisher: SPRINGER-VERLAG BERLIN, Pages: 237-252, ISSN: 1868-4238

CONFERENCE PAPER

Kyrkou C, Bouganis C-S, Theocharides T, Polycarpou MMet al., 2016, Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines, IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS, Vol: 27, Pages: 99-112, ISSN: 2162-237X

JOURNAL ARTICLE

Liu J, Bouganis C, Cheung PYK, 2016, Context-based image acquisition from memory in digital systems, Journal of Real-Time Image Processing, ISSN: 1861-8200

JOURNAL ARTICLE

Mingas G, Bouganis C-S, 2016, Population-Based MCMC on Multi-Core CPUs, GPUs and FPGAs, IEEE TRANSACTIONS ON COMPUTERS, Vol: 65, Pages: 1283-1296, ISSN: 0018-9340

JOURNAL ARTICLE

Rabieah MB, Bouganis C-S, 2016, FPGASVM: A Framework for Accelerating Kernelized Support Vector Machine., BigMine-2016, Publisher: JMLR.org, Pages: 68-84

CONFERENCE PAPER

Vavouras M, Bouganis C-S, 2016, Area-Driven Partial Reconfiguration for SEU Mitigation on SRAM-based FPGAs, International Conference on Reconfigurable Computing and FPGAs (ReConFig), Publisher: IEEE, ISSN: 2325-6532

CONFERENCE PAPER

Venieris SI, Bouganis C-S, 2016, fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs, 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 40-47

CONFERENCE PAPER

, 2016, Applied Reconfigurable Computing - 12th International Symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings, Publisher: Springer

CONFERENCE PAPER

Bin Rabieah M, Bouganis C-S, 2015, FPGA Based Nonlinear Support Vector Machine Training Using an Ensemble Learning, 25th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, ISSN: 1946-1488

CONFERENCE PAPER

Duarte RP, Bouganis C-S, 2015, ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation, ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, Vol: 9, ISSN: 1936-7406

JOURNAL ARTICLE

Jin Y, Bouganis C-S, 2015, Robust Multi-Image Based Blind Face Hallucination, IEEE Conference on Computer Vision and Pattern Recognition (CVPR), Publisher: IEEE, Pages: 5252-5260, ISSN: 1063-6919

CONFERENCE PAPER

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