Imperial College London

DrChristos-SavvasBouganis

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Senior Lecturer
 
 
 
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Contact

 

+44 (0)20 7594 6144christos-savvas.bouganis Website

 
 
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Location

 

904Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
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103 results found

Bouganis C, Boikos K, 2017, A High-Performance System-on-Chip Architecture for Direct Tracking for SLAM, International Conference on Field-Programmable Logic and Applications, Publisher: IEEE, ISSN: 1946-1488

Simultaneous Localization and Mapping or SLAM, is a family of algorithms that solve the problem of estimating an observer's position in an unknown environment while generating a map of that environment. SLAM algorithms that produce high quality dense maps require powerful hardware platforms. In the simultaneous solution of these two problems, Localization, also known as Tracking, is the one that is latency sensitive and needs a sustained high framerate. This work focuses on providing an efficient, high-performance solution for Direct Tracking using a high bandwidth streaming architecture, optimized for maximum memory throughput. At its centre is a Tracking Core that performs non-linear least-squares optimization for direct whole-image alignment. The architecture is designed to scale with the available hardware resources in order to enable its use for different performance/cost levels and platforms. An initial implementation tested with a Zynq System-on-Chip can process and track more than 22 frames/second with an embedded power budget and achieves a 5× improvement over previous work on FPGA SoCs.

CONFERENCE PAPER

Bouganis C, venieris, 2017, Latency-Driven Design for FPGA-based Convolutional Neural Networks, International Conference on Field-Programmable Logic and Applications, Publisher: IEEE, ISSN: 1946-1488

In recent years, Convolutional Neural Networks (ConvNets) have become the quintessential component of several state-of-the-art Artificial Intelligence tasks. Across the spectrum of applications, the performance needs vary significantly, from high-throughput image recognition to the very low-latency requirements of autonomous cars. In this context, FPGAs can provide a potential platform that can be optimally configured based on different performance requirements. However, with the increasing complexity of ConvNet models, the architectural design space becomes overwhelmingly large, asking for principled design flows that address the application-level needs. This paper presents a latency-driven design methodology for mapping ConvNets on FPGAs. The proposed design flow employs novel transformations over a Synchronous Dataflow-based modelling framework together with a latency-centric optimisation procedure in order to efficiently explore the design space targeting low-latency designs. Quantitative evaluation shows large improvements in latency when latency-driven optimisation is in place yielding designs that improve the latency of AlexNet by 73.54× and VGG16 by 5.61× over throughput-optimised designs.

CONFERENCE PAPER

Bouganis C-S, Gorgon M, Bonato V, 2017, Special issue on applied reconfigurable computing, MICROPROCESSORS AND MICROSYSTEMS, Vol: 52, Pages: 1-1, ISSN: 0141-9331

JOURNAL ARTICLE

Liu S, Bouganis CS, 2017, Communication-aware MCMC method for big data applications on FPGAs, Pages: 9-16

© 2017 IEEE. Markov Chain Monte Carlo (MCMC) based methods have been the main tool for Bayesian Inference for some years now, and recently they find increasing applications in modern statistics and machine learning. Nevertheless, with the availability of large datasets and increasing complexity of Bayesian models, MCMC methods are becoming prohibitively expensive for real-world problems. At the heart of these methods, lies the computation of likelihood functions that requires access to all input data points in each iteration of the method. Current approaches, based on data subsampling, aim to accelerate these algorithms by reducing the number of the data points for likelihood evaluations at each MCMC iteration. However the existing work doesn't consider the properties of modern memory hierarchies, but treats the memory as one monolithic storage space. This paper proposes a communication-aware MCMC framework that takes into account the underlying performance of the memory subsystem. The framework is based on a novel subsampling algorithm that utilises an unbiased likelihood estimator based on Probability Proportional-to-Size (PPS) sampling, allowing information on the performance of the memory system to be taken into account during the sampling stage. The proposed MCMC sampler is mapped to an FPGA device and its performance is evaluated using the Bayesian logistic regression model on MNIST dataset. The proposed system achieves a 3.37x speed up over a highly optimised traditional FPGA design, therefore the risk in the estimates based on the generated samples is largely decreased.

CONFERENCE PAPER

Liu S, Mingas G, Bouganis C-S, 2017, An Unbiased MCMC FPGA-Based Accelerator in the Land of Custom Precision Arithmetic, IEEE TRANSACTIONS ON COMPUTERS, Vol: 66, Pages: 745-758, ISSN: 0018-9340

JOURNAL ARTICLE

Mingas G, Bottolo L, Bouganis C-S, 2017, Particle MCMC algorithms and architectures for accelerating inference in state-space models, INTERNATIONAL JOURNAL OF APPROXIMATE REASONING, Vol: 83, Pages: 413-433, ISSN: 0888-613X

JOURNAL ARTICLE

Boikos K, Bouganis C-S, 2016, Semi-Dense SLAM on an FPGA SoC, 26th International Conference on Field-Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488

CONFERENCE PAPER

Duarte RP, Bouganis C-S, 2016, Variation-Aware Optimisation for Reconfigurable Cyber-Physical Systems, 7th IFIP WG 5.5/SOCOLNET Advanced Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Publisher: SPRINGER-VERLAG BERLIN, Pages: 237-252, ISSN: 1868-4238

CONFERENCE PAPER

Kyrkou C, Bouganis C-S, Theocharides T, Polycarpou MMet al., 2016, Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines, IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS, Vol: 27, Pages: 99-112, ISSN: 2162-237X

JOURNAL ARTICLE

Liu J, Bouganis C, Cheung PYK, 2016, Context-based image acquisition from memory in digital systems, Journal of Real-Time Image Processing, ISSN: 1861-8200

JOURNAL ARTICLE

Mingas G, Bouganis C-S, 2016, Population-Based MCMC on Multi-Core CPUs, GPUs and FPGAs, IEEE TRANSACTIONS ON COMPUTERS, Vol: 65, Pages: 1283-1296, ISSN: 0018-9340

JOURNAL ARTICLE

Vavouras M, Bouganis C-S, 2016, Area-Driven Partial Reconfiguration for SEU Mitigation on SRAM-based FPGAs, International Conference on Reconfigurable Computing and FPGAs (ReConFig), Publisher: IEEE, ISSN: 2325-6532

CONFERENCE PAPER

Vavouras M, Duarte RP, Armato A, Bouganis C-Set al., 2016, A Hybrid ASIC/FPGA Fault-Tolerant Artificial Pancreas, International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS), Publisher: IEEE, Pages: 261-267

CONFERENCE PAPER

Venieris SI, Bouganis C-S, 2016, fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs, 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 40-47

CONFERENCE PAPER

Bin Rabieah M, Bouganis C-S, 2015, FPGA Based Nonlinear Support Vector Machine Training Using an Ensemble Learning, 25th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, ISSN: 1946-1488

CONFERENCE PAPER

Duarte RP, Bouganis C-S, 2015, ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation, ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, Vol: 9, ISSN: 1936-7406

JOURNAL ARTICLE

Jin Y, Bouganis C-S, 2015, Robust Multi-Image Based Blind Face Hallucination, IEEE Conference on Computer Vision and Pattern Recognition (CVPR), Publisher: IEEE, Pages: 5252-5260, ISSN: 1063-6919

CONFERENCE PAPER

Liu S, Mingas G, Bouganis C-S, 2015, An Exact MCMC Accelerator Under Custom Precision Regimes, International Conference on Field Programmable Technology (FTP), Publisher: IEEE, Pages: 120-127

CONFERENCE PAPER

Scicluna N, Bouganis C-S, 2015, ARC 2014: A Multidimensional FPGA-Based Parallel DBSCAN Architecture, ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, Vol: 9, ISSN: 1936-7406

JOURNAL ARTICLE

Venieris SI, Mingas G, Bouganis C-S, 2015, Towards Heterogeneous Solvers for Large-Scale Linear Systems, 25th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, ISSN: 1946-1488

CONFERENCE PAPER

Angelopoulou ME, Bouganis C-S, 2014, Vision-Based Egomotion Estimation on FPGA for Unmanned Aerial Vehicle Navigation, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, Vol: 24, Pages: 1070-1083, ISSN: 1051-8215

JOURNAL ARTICLE

Cheng C, Bouganis C-S, 2014, Memory Optimisation for Hardware Induction of Axis-parallel Decision Tree, 2014 International Conference on Reconfigurable Computing and FAGAs, Publisher: IEEE, ISSN: 2325-6532

CONFERENCE PAPER

Duarte RP, Bouganis C-S, 2014, Over-Clocking of Linear Projection Designs Through Device Specific Optimisations, 28th IEEE International Parallel & Distributed Processing Symposium Workshops (IPDPSW), Publisher: IEEE, Pages: 189-198

CONFERENCE PAPER

Duarte RP, Bouganis C-S, 2014, A Unified Framework for Over-Clocking Linear Projections on FPGAs under PVT Variation., Publisher: Springer, Pages: 49-60

CONFERENCE PAPER

Duarte RP, Bouganis C-S, 2014, Zero-Latency Datapath Error Correction Framework for Over-Clocking DSP Applications on FPGAs, 2014 International Conference on Reconfigurable Computing and FAGAs, Publisher: IEEE, ISSN: 2325-6532

CONFERENCE PAPER

Liu J, Bouganis C, Cheung PYK, 2014, Image Progressive Acquisition for Hardware Systems, Design, Automation and Test in Europe Conference and Exhibition (DATE), Publisher: IEEE, ISSN: 1530-1591

CONFERENCE PAPER

Liu J, Bouganis C, Cheung PYK, 2014, Kernel-based Adaptive Image Sampling, 9th International Conference on Computer Vision Theory and Applications (VISAPP), Publisher: IEEE, Pages: 25-32

CONFERENCE PAPER

Liu S, Mingas G, Bouganis C-S, 2014, Parallel Resampling for Particle Filters on FPGAs, International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 191-198

CONFERENCE PAPER

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