Imperial College London


Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Research Assistant







Electrical EngineeringSouth Kensington Campus





Publication Type

8 results found

Haci D, Liu Y, Nikolic K, Demarchi D, Constandinou TG, Georgiou Pet al., 2018, Thermally controlled lab-on-PCB for biomedical applications, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 655-658

This paper reports on the implementation andcharacterisation of a thermally controlled device forin vitrobiomedical applications, based on standard Printed Circuit Board(PCB) technology. This is proposed as a low cost alternativeto state-of-the-art microfluidic devices and Lab-on-Chip (LoC)platforms, which we refer to as the thermal Lab-on-PCB concept.In total, six different prototype boards have been manufacturedto implement as many mini-hotplate arrays. 3D multiphysicssoftware simulations show the thermal response of the modelledmini-hotplate boards to electrical current stimulation, highlight-ing their versatile heating capability. A comparison with theresults obtained by the characterisation of the fabricated PCBsdemonstrates the dual temperature sensing/heating property ofthe mini-hotplate, exploitable in a larger range of temperaturewith respect to the typical operating range of LoC devices. Thethermal system is controllable by means of external off-the-shelfcircuitry designed and implemented on a single-channel controlboard prototype.

Conference paper

Haci D, Liu Y, Ghoreishizadeh S, Constandinou TGet al., 2018, Design considerations for ground referencing in multi-module neural implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference 2018, Publisher: IEEE, Pages: 563-566

Implantable neural interfaces have evolved in thepast decades from stimulation-only devices to closed-loop record-ing and stimulation systems, allowing both for more targetedtherapeutic techniques and more advanced prosthetic implants.Emerging applications require multi-module active implantabledevices with intrabody power and data transmission. Thisdistributed approach poses a new set of challenges relatedto inter-module connectivity, functional reliability and patientsafety. This paper addresses the ground referencing challenge inactive multi-implant systems, with a particular focus on neuralrecording devices. Three different grounding schemes (passive,drive, and sense) are presented and evaluated in terms of bothrecording reliability and patient safety. Considerations on thepractical implementation of body potential referencing circuitryare finally discussed, with a detailed analysis of their impact onthe recording performance.

Conference paper

Ramezani R, Liu Y, Dehkhoda F, Soltan A, Haci D, Zhao H, Hazra A, Cunningham M, Firfilionis D, Jackson A, Constandinou TG, Degenaar Pet al., 2018, On-probe neural interface ASIC for combined electrical recording and optogenetic stimulation, IEEE Transactions on Biomedical Circuits and Systems, Vol: 12, Pages: 576-588, ISSN: 1932-4545

Neuromodulation technologies are progressing from pacemaking and sensory operations to full closed-loop control. In particular, optogenetics—the genetic modification of light sensitivity into neural tissue allows for simultaneous optical stimulation and electronic recording. This paper presents a neural interface application-specified integrated circuit (ASIC) for intelligent optoelectronic probes. The architecture is designed to enable simultaneous optical neural stimulation and electronic recording. It provides four low noise (2.08 μVrms) recording channels optimized for recording local field potentials (LFPs) (0.1–300 Hz bandwidth, ± 5 mV range, sampled 10-bit@4 kHz), which are more stable for chronic applications. For stimulation, it provides six independently addressable optical driver circuits, which can provide both intensity (8-bit resolution across a 1.1 mA range) and pulse-width modulation for high-radiance light emitting diodes (LEDs). The system includes a fully digital interface using a serial peripheral interface (SPI) protocol to allow for use with embedded controllers. The SPI interface is embedded within a finite state machine (FSM), which implements a command interpreter that can send out LFP data whilst receiving instructions to control LED emission. The circuit has been implemented in a commercially available 0.35 μm CMOS technology occupying a 1.95 mm × 1.10 mm footprint for mounting onto the head of a silicon probe. Measured results are given for a variety of bench-top, in vitro and in vivo experiments, quantifying system performance and also demonstrating concurrent recording and stimulation within relevant experimental models.

Journal article

Mifsud A, Haci D, Ghoreishizadeh SS, Liu Y, Constandinou TGet al., 2018, Adaptive power regulation and data delivery for multi-module implants, Pages: 1-4

© 2017 IEEE. Emerging applications for implantable devices are requiring multi-unit systems with intrabody transmission of power and data through wireline interfaces. This paper proposes a novel method for power delivery within such a configuration that makes use of closed loop dynamic regulation. This is implemented for an implantable application requiring a single master and multiple identical slave devices utilising a parallel-connected 4-wire interface. The power regulation is achieved within the master unit through closed loop monitoring of the current consumption to the wired link. Simultaneous power transfer and full-duplex data communication is achieved by superimposing the power carrier and downlink data over two wires and uplink data over a second pair of wires. Measured results using a fully isolated (AC coupled) 4-wire lead, demonstrate this implementation can transmit up to 120 mW of power at 6 V (at the slave device, after eliminating any losses). The master device has a maximum efficiency of 80 % including a dominant dynamic power loss. A 6 V constant supply at the slave device is recovered 1.5 ms after a step of 22 mA.

Conference paper

Mifsud A, Haci D, Ghoreishizadeh S, Liu Y, Constandinou TGet al., 2017, Adaptive Power Regulation and Data Delivery for Multi-Module Implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 584-587

Conference paper

Ghoreishizadeh S, Haci D, Liu Y, Donaldson N, Constandinou TGet al., 2017, Four-Wire Interface ASIC for a Multi-Implant Link, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Pages: 3056-3067, ISSN: 1549-8328

This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical ‘optrodes’ that facilitate a bidirectional neural interface (electrical recording, optical stimulation), and chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate(up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) which is superimposed on a power carrier. On-chip power management provides an unregulated 5V DC supply with up to 2.5mA output current for stimulation, and two regulated voltages (3.3V and 3V) with 60 dB PSRR for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35 um CMOS technology, occupying 1.5mm2 silicon area,and consumes a quiescent current of 91.2u A. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.

Journal article

Haci D, Liu Y, Constandinou TG, 2017, 32-channel ultra-low-noise arbitrary signal generation platform for biopotential emulation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701

This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10kHz bandwidth, 110dB dynamic range and uV-level output noise.

Conference paper

Ghoreishizadeh S, Haci D, Liu Y, Constandinou Tet al., 2017, A 4-wire interface SoC for shared multi-implant power transfer and full-duplex communication, IEEE Latin American symposium on Circuits and Systems (LASCAS), Pages: 49-52

This paper describes a novel system for recoveringpower and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. Thetarget application requires a singleChest Devicebe connectedto aBrain Implantconsisting of multiple identical optrodesthat record neural activity and provide closed loop opticalstimulation. The interface is integrated within each optrode SoCallowing full-duplex and fully-differential communication basedon Manchester encoding. The system features a head-to-chestuplink data rate (1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) superimposed on a power carrier.On-chip power management provides an unregulated 5 V DCsupply with up to 2.5 mA output current for stimulation, anda regulated 3.3 V with 60 dB PSRR for recording and logiccircuits. The circuit has been implemented in a 0.35μm CMOStechnology, occupying 1.4 mm2silicon area, and requiring a62.2μA average current consumption.

Conference paper

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