Imperial College London


Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Senior Lecturer



+44 (0)20 7594 6303d.thomas1 Website




903Electrical EngineeringSouth Kensington Campus





Hello! I'm David Thomas and am a lecturer in this fine department. I'm part of the Circuits and Systems research group in EEE, which means I'm on level 9 of the EEE building, and more specifically in room 903.


 I currently teach three courses:

  • Language Processors (EE2-15) : an introduction to automata theory and compiler design, resulting in the creation of a C compiler, taken by EIE students in the second year.
  • Computer Architecture (C210=EE2-13) : an introduction to CPU design, taken by both EIE and Computing students in the second year.
  • High Performance Computing for Engineers (EE4-63) : tries to get people up and running with practical multi-core and GPU programming, without most of the pain of parallel programming. Currently available to 4th years from EEE, EIE, and the ADIC MSc programme

I am also the course director for the Electronic and Information Engineering degree course (previously called Information Systems Engineering (ISE)).


Within the Circuits and Systems group I run the Accelerated Numerics research group. This group mostly explores ways in which accelerators such as FPGAs and GPUs can be used to accelerate compute-intensive numerical calculations, such as in computational finance (though more recently this has started to encompass data-oriented processing as well). My particular interest is in trying to rethink algorithms and applications to take advantage of hardware, rather than trying to force existing software algorithms and C code into an FPGA.

In 2016 I am hosting ASAP 2016



Tavakkoli A, Thomas DB, 2018, A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers, Ieee Transactions on Very Large Scale Integration (vlsi) Systems, Vol:26, ISSN:1063-8210, Pages:341-354

Fabry P, Thomas D, 2017, Efficient Reconfigurable Architecture for Pricing Exotic Options, Acm Transactions on Reconfigurable Technology and Systems, Vol:10, ISSN:1936-7406

Wijeyasinghe M, Thomas D, 2017, Combining hardware and software codecs to enhance data channels in FPGA streaming systems, Microprocessors and Microsystems, Vol:51, ISSN:0141-9331, Pages:275-288


Fleming ST, Thomas DB, 2017, Using Runahead Execution to Hide Memory Latency in High Level Synthesis, 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, Pages:109-116

Tarawneh G, Mokhov A, Naylor M, et al., 2017, Programming Model to Develop Supercomputer Combinatorial Solvers, 46th International Conference on Parallel Processing Workshops (ICPPW), IEEE, Pages:171-179, ISSN:1530-2016

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