99 results found
Fleming S, Beretta I, Constantinides G, et al., PushPush: Seamless integration of hardware and software objects via function calls over AXI, FPL
Fleming S, Thomas DB, Constantinides G, et al., System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System, FPGA
Shao S, Guo L, Guo C, et al., Recursive pipelined genetic propagation for bilevel optimisation, FPL
Inggs G, Thomas DB, Luk W, 2017, A Domain Specific Approach to High Performance Heterogeneous Computing, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, Vol: 28, Pages: 2-15, ISSN: 1045-9219
Wijeyasinghe M, Thomas D, 2017, Combining hardware and software codecs to enhance data channels in FPGA streaming systems, MICROPROCESSORS AND MICROSYSTEMS, Vol: 51, Pages: 275-288, ISSN: 0141-9331
Fleming ST, Thomas DB, 2016, StitchUp: Automatic Control Flow Protection for High Level Synthesis Circuits, 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Publisher: ASSOC COMPUTING MACHINERY
Fleming ST, Thomas DB, 2016, StitchUp: Automatic Control Flow Protection for High Level Synthesis Circuits, 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Publisher: IEEE, ISSN: 0738-100X
Ogden P, Thomas D, Pietzuch P, 2016, AT-GIS: Highly parallel spatial query processing with associative transducers, Pages: 1041-1054, ISSN: 0730-8078
© 2016 ACM. Users in many domains, including urban planning, transportation, and environmental science want to execute analytical queries over continuously updated spatial datasets. Current solutions for largescale spatial query processing either rely on extensions to RDBMS, which entails expensive loading and indexing phases when the data changes, or distributed map/reduce frameworks, running on resource-hungry compute clusters. Both solutions struggle with the sequential bottleneck of parsing complex, hierarchical spatial data formats, which frequently dominates query execution time. Our goal is to fully exploit the parallelism offered by modern multicore CPUs for parsing and query execution, thus providing the performance of a cluster with the resources of a single machine. We describe AT-GIS, a highly-parallel spatial query processing system that scales linearly to a large number of CPU cores. ATGIS integrates the parsing and querying of spatial data using a new computational abstraction called associative transducers (ATs). ATs can form a single data-parallel pipeline for computation without requiring the spatial input data to be split into logically independent blocks. Using ATs, AT-GIS can execute, in parallel, spatial query operators on the raw input data in multiple formats, without any pre-processing. On a single 64-core machine, AT-GIS provides 3× the performance of an 8-node Hadoop cluster with 192 cores for containment queries, and 10× for aggregation queries.
Salem V, Izzi-Engbeaya C, Coello C, et al., 2016, Glucagon increases energy expenditure independently of brown adipose tissue activation in humans, DIABETES OBESITY & METABOLISM, Vol: 18, Pages: 72-81, ISSN: 1462-8902
Su J, Thomas DB, Cheung PYK, 2016, Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines using Dropout, 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 48-51
Thomas DB, 2016, Synthesisable Recursion for C plus plus HLS Tools, 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Publisher: IEEE, Pages: 91-98, ISSN: 1063-6862
Xue Z, Thomas DB, 2016, SynADT: Dynamic Data Structures in High Level Synthesis, 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 64-71
Fleming ST, Beretta I, Thomas DB, et al., 2015, PushPush: Seamless Integration of Hardware and Software Objects Via Function Calls over AXI, 25th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, ISSN: 1946-1488
Fleming ST, Thomas DB, Constantinides GA, et al., 2015, System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System., Publisher: ACM, Pages: 214-217
Guo L, Funie AI, Xie Z, et al., 2015, A general-purpose framework for FPGA-accelerated genetic algorithms, INTERNATIONAL JOURNAL OF BIO-INSPIRED COMPUTATION, Vol: 7, Pages: 361-375, ISSN: 1758-0366
Guo L, Guo C, Thomas DB, et al., 2015, Pipelined Genetic Propagation, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 103-110
Inggs G, Thomas DB, Constantinides GA, et al., 2015, Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service.
Inggs G, Thomas DB, Luk W, 2015, An Efficient, Automatic Approach to High Performance Heterogeneous Computing., CoRR, Vol: abs/1505.04417
Shao S, Guo L, Guo C, et al., 2015, Recursive Pipelined Genetic Propagation for Bilevel Optimisation, 25th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, ISSN: 1946-1488
Thomas DB, 2015, A general-purpose method for faithfully rounded floating-point function approximation in FPGAs, IEEE 22nd Symposium on Computer Arithmetic ARITH 22, Publisher: IEEE, Pages: 42-49, ISSN: 1063-6889
Thomas DB, 2015, The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator, ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, Vol: 8, ISSN: 1936-7406
Thomas DB, Fleming ST, Constantinides GA, et al., 2015, Transparent linking of compiled software and synthesized hardware, Conference on Design Automation Test in Europe (DATE), Publisher: IEEE, Pages: 1084-1089, ISSN: 1530-1591
Xue Z, Thomas DB, 2015, SysAlloc: A Hardware Manager for Dynamic Memory Allocation in Heterogeneous Systems, 25th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, ISSN: 1946-1488
Aguilar-Pelaez E, Bayliss S, Smith A, et al., 2014, Compiling Higher Order Functional Programs to Composable Digital Hardware, 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines ((FCCM), Publisher: IEEE, Pages: 234-234
Gallo L, Cilardo A, Thomas DB, et al., 2014, Area implications of memory partitioning for high-level synthesis on FPGAs., Publisher: IEEE, Pages: 1-4
Guo L, Thomas DB, Guo C, et al., 2014, Automated framework for FPGA-based parallel genetic algorithms
© 2014 Technical University of Munich (TUM). Parallel genetic algorithms (pGAs) are a variant of genetic algorithms which can promise substantial gains in both efficiency of execution and quality of results. pGAs have attracted researchers to implement them in FPGAs, but the implementation always needs large human effort. To simplify the implementation process and make the hardware pGA designs accessible to potential non-expert users, this paper proposes a general-purpose framework, which takes in a high-level description of the optimisation target and automatically generates pGA designs for FPGAs. Our pGA system exploits the two levels of parallelism found in GA instances and genetic operations, allowing users to tailor the architecture for resource constraints at compile-time. The framework also enables users to tune a subset of parameters at run-time without time-consuming recompilation. Our pGA design is more flexible than previous ones, and has an average speedup of 26 times compared to the multi-core counterparts over five combinatorial and numerical optimisation problems. When compared with a GPU, it also shows a 6.8 times speedup over a combinatorial application.
Guo L, Thomas DB, Luk W, 2014, Automated Framework for General-Purpose Genetic Algorithms in FPGAs, 17th European Conference on Applications of Evolutionary Computation (EvpApplications), Publisher: SPRINGER-VERLAG BERLIN, Pages: 714-725, ISSN: 0302-9743
Guo L, Thomas DB, Luk W, 2014, Customisable architectures for the set covering problem, ACM SIGARCH Computer Architecture News, Vol: 41, Pages: 101-106, ISSN: 0163-5964
Inggs G, Fleming S, Thomas D, et al., 2014, Is High Level Synthesis ready for business? A computational finance case study, International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 12-19
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