Imperial College London

DrDeren YusufBarsakcioglu

Faculty of EngineeringDepartment of Bioengineering

Research Associate







B121Bessemer BuildingSouth Kensington Campus





Publication Type

7 results found

Barsakcioglu DY, Farina D, 2018, A real-time surface EMG decomposition system for non-invasive human-machine interfaces, IEEE Biomedical Circuits and Systems Conference (BioCAS), Publisher: IEEE, ISSN: 2163-4025

Real-time surface EMG decomposition, to extract neural activity of spinal motor neurons, provides a non-invasive solution for establishing direct interfaces with the central nervous system. In this paper, we present a real-time EMG decomposition system, validate it through both synthetic and experimental high-density surface EMG (HD-sEMG) data, and demonstrate the system in an upper-limb prosthetic control scenario. The proposed system achieves (in real-time) median decomposition accuracy comparable to offline methods (within 0.5 %) with minimal utilisation of computational resources (x20 faster compared to the literature).

Conference paper

Dávila-Montero S, Barsakcioglu DY, Jackson A, Constandinou TG, Mason AJet al., 2017, Real-time clustering algorithm that adapts to dynamic changes in neural recordings, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 690-693

This work presents a computationally efficient real-time adaptive clustering algorithm that recognizes and adapts to dynamic changes observed in neural recordings. The algorithm consists of an off-line training phase that determines initial cluster positions, and an on-line operation phase that continuously tracks drifts in clusters and periodically verifies acute changes in cluster composition. Analysis of chronic recordings from non-human primates shows that adaptive clustering achieves an improvement of 14% in classification accuracy and demonstrates an ability to recognize acute changes with 78% accuracy, with up to 29% computational efficiency compared to the state-of-the-art. The presented algorithm is suitable for long-term chronic monitoring of neural activity in various applications such as neuroscience research and control of neural prosthetics and assistive devices.

Conference paper

Barsakcioglu DY, Constandinou TG, 2016, A 32-Channel MCU-Based Feature Extraction and Classification for Scalable on-Node Spike Sorting, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1310-1313

This paper describes a new hardware-efficientmethod and implementation for neural spike sorting basedon selection of a channel-specific near-optimal subset of fea-tures given a larger predefined set. For each channel, real-time classification is achieved using a simple decision matrixthat considers the features that provide the highest separabilitydetermined through off-line training. A 32-channel system for on-line feature extraction and classification has been implementedin an ARM Cortex-M0+ processor. Measured results of thehardware platform consumes 268 W per channel during spikesorting (includes detection). The proposed method provides atleast x10 reduction in computational requirements compared toliterature, while achieving an average classification error of lessthan 10% across wide range of datasets and noise levels.

Conference paper

Barsakcioglu D, Liu Y, Bhunjun P, Navajas J, Eftekhar A, Jackson A, Quian Quiroga R, Constandinou TGet al., 2014, An Analogue Front-End Model for Developing Neural Spike Sorting Systems, IEEE Transactions on Biomedical Circuits and Systems, Vol: 8, Pages: 216-227

Journal article

Navajas J, Barsakcioglu D, Eftekhar A, Jackson A, Constandinou TG, Quian Quiroga Ret al., 2014, Minimum Requirements for Accurate and Efficient Real-Time On-Chip Spike Sorting, Journal of Neuroscience Methods, Pages: 51-64

Journal article

Barsakcioglu DY, Eftekhar A, Constandinou TG, 2013, Design Optimisation of Front-End Neural Interfaces for Spike Sorting Systems, IEEE International Symposium on Circuits and Systems (ISCAS)

This work investigates the impact of the analoguefront-end design (pre-amplifier, filter and converter) on spike sorting performance in neural interfaces. By examining key design parameters including the signal-to-noise ratio, bandwidth,filter type/order, data converter resolution and sampling rate, their sensitivity to spike sorting accuracy is assessed. This is applied to commonly used spike sorting methods such as template matching, 2nd derivative-features, and principle component analysis. The results reveal a near optimum set of parameters to increase performance given the hardware-constraints. Finally, the relative costs of these design parameters on resource efficiency (silicon area and power requirements) are quantified through reviewing the state-of-the-art.

Conference paper

Paraskevopoulou SE, Barsakcioglu D, Saberi M, Eftekhar A, Constandinou TGet al., 2013, Feature Extraction using First and Second Derivative Extrema (FSDE), for Real-time and Hardware-Efficient Spike Sorting, Journal of Neuroscience Methods, Vol: 215, Pages: 29-37, ISSN: 0165-0270

Next generation neural interfaces aspire to achieve real-time multi-channel systems by integrating spike sorting on chip to overcome limitations in communication channel capacity. The feasibility of this approach relies on developing highly-efficient algorithms for feature extraction and clustering with the potential of low-power hardware implementation. We are proposing a feature extraction method, not requiring any calibration, based on first and second derivative features of the spike waveform. The accuracy and computational complexity of the proposed method are quantified and compared against commonly used feature extraction methods, through simulation across four datasets (with different single units) at multiple noise levels (ranging from 5 to 20% of the signal amplitude). The average classification error is shown to be below 7% with a computational complexity of 2N-3, where N is the number of sample points of each spike. Overall, this method presents a good trade-off between accuracy and computational complexity and is thus particularly well-suited for hardware-efficient implementation.

Journal article

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