James Davis is a Teaching Fellow in the Department of Electrical and Electronic Engineering's Circuits and Systems group at Imperial College London. For 2018–19, he leads the department's Computer Architecture 2 and High-performance Computing modules.
His research interests include:
- Runtime monitoring of digital electronic hardware
- Computer arithmetic
- Neural network inference
- Fault tolerance, reliability and lifetime extension
- Self-adaptive systems
- Reconfigurable computing
- Heterogeneous and embedded systems.
James serves on the technical programme committees of the four top-tier reconfigurable computing conferences (FPGA, FCCM, FPL and FPT) and is a multi-best paper award recipient. He is a Member of the IEEE and ACM.
et al., 2019, Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going, Acm Computing Surveys, Vol:52, ISSN:0360-0300, Pages:40:1-40:39
et al., LUTNet: Rethinking Inference in FPGA Soft Logic, IEEE Symposium on Field-programmable Custom Computing Machines (FCCM) 2019, IEEE
et al., 2018, Digit Elision for Arbitrary-accuracy Iterative Computation, IEEE Symposium on Computer Arithmetic (ARITH) 2018, IEEE, Pages:107-114
Wang E, Davis JJ, Cheung P, 2018, A PYNQ-based Framework for Rapid CNN Prototyping, IEEE Symposium on Field-programmable Custom Computing Machines (FCCM) 2018, IEEE, Pages:223-223
et al., 2018, Hardware Compilation of Deep Neural Networks: An Overview (invited), IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018, IEEE, Pages:1-8