James Davis is a Research Fellow in the Department of Electrical and Electronic Engineering's Circuits and Systems group at Imperial College London.
His research interests include:
- Runtime monitoring of digital electronic hardware
- Computer arithmetic
- Neural network inference
- Fault tolerance, reliability and lifetime extension
- Self-adaptive systems
- Reconfigurable computing
- Heterogeneous and embedded systems.
James serves on the technical programme committees of the four top-tier reconfigurable computing conferences (FPGA, FCCM, FPL and FPT) and is a multi-best paper award recipient. He is a Member of the IEEE and ACM.
et al., 2020, Digit stability inference for iterative methods using redundant number representation, Ieee Transactions on Computers, ISSN:0018-9340
et al., 2020, LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference, Ieee Transactions on Computers, ISSN:0018-9340
et al., 2019, ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute, Ieee Transactions on Very Large Scale Integration (vlsi) Systems, Vol:28, ISSN:1063-8210, Pages:516-529
et al., 2019, Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going, Acm Computing Surveys, Vol:52, ISSN:0360-0300, Pages:40:1-40:39
et al., 2019, LUTNet: Rethinking Inference in FPGA Soft Logic, IEEE Symposium on Field-programmable Custom Computing Machines (FCCM) 2019, IEEE, Pages:26-34