James Davis is a Teaching Fellow in the Department of Electrical and Electronic Engineering's Circuits and Systems group at Imperial College London. For 2018–19, he leads the department's Computer Architecture 2 and High-performance Computing modules.
His research interests include:
- Runtime monitoring of digital electronic hardware
- Computer arithmetic
- Fault tolerance, reliability and lifetime extension
- Self-adaptive systems
- Reconfigurable computing
- Heterogeneous and embedded systems.
James serves on the technical programme committees of the four top-tier reconfigurable computing conferences (FPGA, FCCM, FPL and FPT) and is a multi-best paper award recipient. He is a Member of the IEEE and ACM.
et al., 2018, Digit Elision for Arbitrary-accuracy Iterative Computation, IEEE Symposium on Computer Arithmetic (ARITH) 2018, IEEE, Pages:107-114
Wang E, Davis JJ, Cheung P, 2018, A PYNQ-based Framework for Rapid CNN Prototyping, IEEE Symposium on Field-programmable Custom Computing Machines (FCCM) 2018, IEEE, Pages:223-223
et al., 2018, Hardware Compilation of Deep Neural Networks: An Overview (invited), IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018, IEEE, Pages:1-8
et al., 2018, An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems, International Joint Conference on Pervasive and Embedded Computing and Communication Systems (PECCS) 2018, SciTePress, Pages:57-66
et al., 2018, KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications, International Workshop on OpenCL (IWOCL) 2018, ACM, Pages:4:1-4:1