Imperial College London
Professor Nobuko Yoshida

ProfessorNobukoYoshida

Faculty of Engineering, Department of Computing

Academic Visitor
 
 
 
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Contact

 

+44 (0)20 7594 8240n.yoshida Website

 
 
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Location

 

556Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Niu:2016:10.1109/FPL.2016.7577359,
author = {Niu, X and Ng, C and Yumi, T and Wang, S and Yoshida, N and Luk, W},
doi = {10.1109/FPL.2016.7577359},
publisher = {IEEE},
title = {EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits},
url = {http://dx.doi.org/10.1109/FPL.2016.7577359},
year = {2016}
}
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RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - EURECA  architectures  have  been  proposed  as  anenhancement  to  the  existing  FPGAs,  to  enable  cycle-by-cyclereconfiguration. Applications with irregular data accesses, whichpreviously   cannot   be   efficiently   supported   in   hardware,   canbe  efficiently  mapped  into  EURECA  architectures.  One  majorchallenge   to   apply   the   EURECA   architectures   to   practicalapplications  is  the  intensive  design  efforts  required  to  analyseand optimise cycle-reconfigurable operations, in order to obtainaccurate and high-performance results while underlying circuitsreconfigure  cycle  by  cycle.  In  this  work,  we  propose  compilersupport   for   EURECA-based   designs.   The   compiler   supportadopts techniques based on session types to automatically derive aruntime reconfiguration scheduler that guarantees design correct-ness; and a streaming circuit model to ensure high-performancecircuits.   Three   benchmark   applications   —large-scale   sorting,Memcached, and SpMV— developed with the proposed compilersupport  show  up  to  11.2  times  (21.8  times  when  architecturescales)  reduction  in  area-delay  product  when  compared  withconventional architectures, and achieve up to39%improvementscompared  with  manually  optimised  EURECA  designs.
AU  - Niu,X
AU  - Ng,C
AU  - Yumi,T
AU  - Wang,S
AU  - Yoshida,N
AU  - Luk,W
DO  - 10.1109/FPL.2016.7577359
PB  - IEEE
PY  - 2016///
TI  - EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits
UR  - http://dx.doi.org/10.1109/FPL.2016.7577359
UR  - https://ieeexplore.ieee.org/document/7577359
UR  - http://hdl.handle.net/10044/1/34334
ER  -
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