Imperial College London

ProfessorPeterCheung

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Professor of Digital Systems
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

617Electrical EngineeringSouth Kensington Campus

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Summary

 

Summary

Peter Y. K. Cheung is Professor of Digital Systems and Head of the Department of Electrical and Electronic Engineering.  He is also Vice Dean (Education) of the Faculty of Engineering at Imperial College London.  Together with Professor Wayne Luk in Department of Computing, he established one of the strongest research groups in the area of Field Programmable Gate Arrays (FPGAs) in the UK.  His research in reconfigurable systems and technology include architecture, variability mitigation, reliability issues, high-level synthesis and tools, and various application area for FPGAs. 

For details of research and teaching activities, please visit:

www.ee.ic.ac.uk/pcheung/

Selected Publications

Journal Articles

Ang S-S, Constantinides GA, Luk W, et al., 2008, Custom parallel caching schemes for hardware-accelerated image compression, Journal of Real-Time Image Processing, Vol:3, ISSN:1861-8200, Pages:289-302

Bouganis C-S, Park S-B, Constantinides GA, et al., 2009, Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs, ACM Transactions on Reconfigurable Technology and Systems, Vol:1, ISSN:1936-7406, Pages:1-28

Liu Y, Bouganis C-S, Cheung PYK, 2009, Hardware architectures for eigenvalue computation of real symmetric matrices, IET Computers and Digital Techniques, Vol:3, ISSN:1751-8601, Pages:72-84

Stott E, Guan Z, Levine JM, et al., 2013, Variation and Reliability in FPGAs, Ieee Design & Test, Vol:30, ISSN:2168-2356, Pages:50-59

Powell A, Savvas-Bouganis C, Cheung PYK, 2013, High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration, Journal of Systems Architecture, Vol:59, ISSN:1383-7621, Pages:1144-1156

Wong JSJ, Cheung PYK, 2013, Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol:21, ISSN:1063-8210, Pages:2307-2320

Liu Q, Constantinides GA, Masselos K, et al., 2009, Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol:28, ISSN:0278-0070, Pages:305-315

Smith AM, Constantinides GA, Cheung PYK, 2010, An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays, ACM Transactions on Reconfigurable Technology and Systems, Vol:3, ISSN:1936-7406

Liu Q, Constantinides GA, Masselos K, et al., 2009, Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems, IET Computers and Digital Techniques, Vol:3, ISSN:1751-8601, Pages:235-246

Kahoul A, Smith AM, Constantinides GA, et al., 2010, Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods, ACM Transactions on Reconfigurable Technology and Systems, Vol:4, ISSN:1936-7406

Smith AM, Constantinides GA, Cheung PYK, 2010, FPGA Architecture Optimization Using Geometric Programming, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol:29, ISSN:0278-0070, Pages:1163-1176

Smith AM, Constantinides GA, Cheung PYK, 2008, Integrated floorplanning, module-selection, and architecture generation for reconfigurable devices, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol:16, ISSN:1063-8210, Pages:733-744

Clarke JA, Constantinides GA, Cheung PYK, 2009, Word-Length Selection for Power Minimization via Nonlinear Optimization, ACM Transactions on Design Automation of Electronic Systems, Vol:14, ISSN:1084-4309

Liu Q, Constantinides GA, Masselos K, et al., 2011, Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization, Computer Journal, Vol:54, ISSN:0010-4620, Pages:1-10

Angelopoulou ME, Bouganis C-S, Cheung PYK, et al., 2009, Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement, ACM Transactions on Reconfigurable Technology and Systems, Vol:2, ISSN:1936-7406

Bouganis C-S, Pournara I, Cheung PYK, 2010, Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol:18, ISSN:1063-8210, Pages:436-449

Angelopoulou ME, Bouganis C-S, Cheung PYK, 2011, Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array, IET Computers and Digital Techniques, Vol:5, ISSN:1751-8601, Pages:271-286

Arifin S, Cheung PYK, 2008, Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information, IEEE Transactions on Multimedia, Vol:10, ISSN:1520-9210, Pages:1325-1341

Mak T, Cheung PYK, Lam K-P, et al., 2011, Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network, IEEE Transactions on Industrial Electronics, Vol:58, ISSN:0278-0046, Pages:3701-3716

Sedcole P, Cheung PYK, 2008, Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations, ACM Transactions on Reconfigurable Technology and Systems, Vol:1, ISSN:1936-7406, Pages:1-28

Wong JSJ, Sedcole P, Cheung PYK, 2009, Self-Measurement of Combinatorial Circuit Delays in FPGAs, ACM Transactions on Reconfigurable Technology and Systems, Vol:2, ISSN:1936-7406

Mak T, Sedcole P, Cheung PYK, et al., 2010, Wave-pipelined intra-chip signaling for on-FPGA communications, Integration-the VLSI Journal, Vol:43, ISSN:0167-9260, Pages:188-201

Becker T, Jamieson P, Luk W, et al., 2010, Power characterisation for fine-grain reconfigurable fabrics, International Journal of Reconfigurable Computing, Vol:2010, ISSN:1687-7195

Jamieson P, Becker T, Cheung PYK, et al., 2010, Benchmarking and Evaluating Reconfigurable Architectures Targeting the Mobile Domain, ACM Transactions on Design Automation of Electronic Systems, Vol:15, ISSN:1084-4309

Turkington K, Constantinides GA, Masselos K, et al., 2008, Outer loop pipelining for application specific datapaths in FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol:16, ISSN:1063-8210, Pages:1268-1280

Fahmy SA, Cheung PYK, Luk W, 2009, High-throughput one-dimensional median and weighted median filters on FPGA, IET Computers and Digital Techniques, Vol:3, ISSN:1751-8601, Pages:384-394

Cope B, Cheung PYK, Luk W, et al., 2010, Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study, IEEE Transactions on Computers, Vol:59, ISSN:0018-9340, Pages:433-448

Chapters

Liu Y, Bouganis C, Cheung PYK, 2008, Real-Time Spatiotemporal Saliency, Next generation artificial vision systems, Editor(s): Bharath, Petrou, Artech House Publishers, ISBN:9781596932241

Conference

Stott EA, Wong JSJ, Sedcole P, et al., 2010, Degradation in FPGAs: Measurement and Modelling, 18th ACM International Symposium on Field-Programmable Gate Arrays, ASSOC COMPUTING MACHINERY, Pages:229-238

Wong JSJ, Sedcole P, Cheung PYK, 2008, A Transition Probability Based Delay Measurement Method for Arbitrary Circuits on FPGAs, International Conference on Field-Programmable Technology, IEEE, Pages:105-112

Angelopoulou ME, Cheung PYK, Masselos K, et al., 2008, Implementation and comparison of the 5/3 lifting 2D discrete wavelet transform computation schedules on FPGAs, 5th IEEE International Conference on Field Programmable Technology, SPRINGER, Pages:3-21, ISSN:1939-8018

Mak T, Sedcole P, Cheung PYK, et al., 2008, Interconnection Lengths and Delays Estimation for Communication Links in FPGAs, ACM International Workshop on System Level Interconnect Prediction, ASSOC COMPUTING MACHINERY, Pages:1-9

Mak T, D'Alessandro C, Sedcole P, et al., 2008, Global Interconnections in FPGAs: Modeling and Performance Analysis, ACM International Workshop on System Level Interconnect Prediction, ASSOC COMPUTING MACHINERY, Pages:51-58

Turkington K, Constantinides GA, Cheung PYK, et al., 2008, Co-optimisation of Datapath and Memory in Outer Loop Pipelining, International Conference on Field-Programmable Technology, IEEE, Pages:1-+

Kahoul A, Constantinides GA, Smith AM, et al., 2009, Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep, 5th International Workshop on Applied Reconfigurable Computing, SPRINGER-VERLAG BERLIN, Pages:133-144, ISSN:0302-9743

Sedcole P, Stott E, Cheung PYK, 2009, COMPENSATING FOR VARIABILITY IN FPGAS BY RE-MAPPING AND RE-PLACEMENT, 19th International Conference on Field Programmable Logic and Applications, IEEE, Pages:613-616, ISSN:1946-1488

Stott E, Sedcole P, Cheung PYK, 2008, FAULT TOLERANT METHODS FOR RELIABILITY IN FPGAs, 18th International Conference on Field Programmable and Logic Applications, IEEE, Pages:414-419, ISSN:1946-1488

Wong JSJ, Cheung PYK, Sedcole P, 2008, COMBATING PROCESS VARIATION ON FPGAS WITH A PRECISE AT-SPEED DELAY MEASUREMENT METHOD, International Conference on Field Programmable and Logic Applications, IEEE, Pages:702-703

Liu Q, Constantinides GA, Masselos K, et al., 2008, COMBINING DATA REUSE EXPLOITATION WITH DATA-LEVEL PARALLELIZATION FOR FPGA TARGETED HARDWARE COMPILATION: A GEOMETRIC PROGRAMMING FRAMEWORK, 18th International Conference on Field Programmable and Logic Applications, IEEE, Pages:179-+, ISSN:1946-1488

Angelopoulou ME, Bouganis C-S, Cheung PYK, et al., 2008, FPGA-based real-time super-resolution on an adaptive image sensor, 4th International Workshop on Applied Reconfigurable Computing, SPRINGER-VERLAG BERLIN, Pages:125-136, ISSN:0302-9743

Sedcole P, Wong JS, Cheung PYK, 2008, Modelling and Compensating for Clock Skew Variability in FPGAs, International Conference on Field-Programmable Technology, IEEE, Pages:217-224

Mak T, Sedcole P, Cheung PYK, et al., 2008, Wave-Pipelined Signaling for On-FPGA Communication, International Conference on Field-Programmable Technology, IEEE, Pages:9-+

Wang L, Mak T, Sedcole P, et al., 2009, Throughput Maximization for Wave-Pipelined Interconnects Using Cascaded Buffers and Transistor Sizing, IEEE International Symposium on Circuits and Systems (ISCAS 2009), IEEE, Pages:1293-1296

Smith AM, Constantinides GA, Cheung PYK, 2009, AREA ESTIMATION AND OPTIMISATION OF FPGA ROUTING FABRICS, 19th International Conference on Field Programmable Logic and Applications, IEEE, Pages:256-261, ISSN:1946-1488

Becker T, Jamieson P, Luk W, et al., 2009, POWER CHARACTERISATION FOR THE FABRIC IN FINE-GRAIN RECONFIGURABLE ARCHITECTURES, 5th Southern Conference on Programmable Logic, IEEE, Pages:77-+

Wong JSJ, Cheung PYK, 2011, Improved Delay Measurement Method in FPGA based on Transition Probability, 19th Annual ACM International Symposium on Field-Programmable Gate Arrays, ASSOC COMPUTING MACHINERY, Pages:163-172

Becker T, Jamieson P, Luk W, et al., 2008, TOWARDS BENCHMARKING ENERGY EFFICIENCY OF RECONFIGURABLE ARCHITECTURES, 18th International Conference on Field Programmable and Logic Applications, IEEE, Pages:690-+, ISSN:1946-1488

Cope B, Cheung PYK, Luk W, 2008, Using reconfigurable logic to optimise GPU memory accesses, Design, Automation and Test in Europe Conference and Exhibition (DATE 08), IEEE, Pages:42-+, ISSN:1530-1591

Becker T, Luk W, Cheung PYK, 2009, Parametric Design for Reconfigurable Software-Defined Radio, 5th International Workshop on Applied Reconfigurable Computing, SPRINGER-VERLAG BERLIN, Pages:15-+, ISSN:0302-9743

Jones DH, Powell A, Bouganis C-S, et al., 2010, A Salient Region Detector for GPU Using a Cellular Automata Architecture, 17th International Conference on Neural Information Processing, SPRINGER-VERLAG BERLIN, Pages:501-508, ISSN:0302-9743

Angelopoulou ME, Bouganis C-S, Cheung PYK, 2009, A SENSOR-BASED APPROACH TO LINEAR BLUR IDENTIFICATION FOR REAL-TIME VIDEO ENHANCEMENT, 16th IEEE International Conference on Image Processing, IEEE, Pages:141-144

Jamieson P, Becker T, Luk W, et al., 2009, Benchmarking Reconfigurable Architectures in the Mobile Domain, 17th Annual IEEE Symposium on Field Programmable Custom Computing Machines, IEEE COMPUTER SOC, Pages:131-+

Angelopoulou ME, Bouganis C-S, Cheung PYK, 2008, VIDEO ENHANCEMENT ON AN ADAPTIVE IMAGE SENSOR, 15th IEEE International Conference on Image Processing (ICIP 2008), IEEE, Pages:681-684, ISSN:1522-4880

Angelopoulou ME, Bouganis C-S, Cheung PYK, 2008, VIDEO ENHANCEMENT ON AN ADAPTIVE IMAGE SENSOR, 15th IEEE International Conference on Image Processing (ICIP 2008), IEEE, Pages:685-688, ISSN:1522-4880

Levine JM, Stott E, Constantinides GA, et al., 2012, Online Measurement of Timing in Circuits: for Health Monitoring and Dynamic Voltage & Frequency Scaling, 20th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, Pages:109-116

Becker T, Jamieson P, Luk W, et al., 2008, Towards benchmarking energy efficiency of reconfigurable architectures, Pages:691-694

Mak STS, Sedcole P, Cheung PYK, et al., 2008, Interconnection lengths and delays estimation for communication links in FPGAs, The 2008 international workshop on System level interconnect prediction, ACM, Pages:1-10

Clarke JA, Constantinides GA, Cheung PYK, et al., 2008, Glitch-aware output switching activity from word-level statistics, IEEE International Symposium on Circuits and Systems, IEEE, Pages:1792-1795, ISSN:0271-4302

Angelopoulou M, Bouganis C, Cheung P, et al., 2008, FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor, Pages:125-136

Cope B, Cheung PYK, Luk W, 2008, Using reconflgurable logic to optimise GPU memory accesses, Pages:44-49, ISSN:1530-1591

Patents

Cheung PYK, Sedcole NP, Wong JS, 2011, Method of Measuring Delay in An Integrated Circuit, USA, US 0095768 A1

More Publications