Publications
349 results found
Sedcole P, Cheung PYK, 2008, Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations, ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol: 1, ISSN: 1936-7406
Variations in the semiconductor fabrication process results in differences in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. Field-Programmable Gate Arrays may be able to compensate for within-die delay variability, by judicious use of reconfigurability. This article presents two strategies for compensating within-die stochastic delay variability by using reconfiguration: reconfiguring the entire FPGA, and relocating subcircuits within an FPGA. Analytical models for the theoretical bounds on the achievable gains are derived for both strategies and compared to models for worst-case design as well as statistical static timing analysis (SSTA). All models are validated by comparison to circuit-level Monte Carlo simulations. It is demonstrated that significant improvements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques.
Mak STS, Sedcole P, Cheung PYK, et al., 2008, Interconnection lengths and delays estimation for communication links in FPGAs, The 2008 international workshop on System level interconnect prediction, Publisher: ACM, Pages: 1-10
This paper presents a new stochastic model to predict interconnection lengths of communication links in FPGAs. Based on a stochastic inter-module routing model, expected length and variance of interconnections have been rigorously derived and, thus, delay can be computed based on the length estimate. The theoretical results are compared with experimental results of lengths and delays, which are obtained from implementations of links circuits in an FPGA. The stochastic model provides an accurate prediction of length with an average error of 6.3%. Results also show that the proposed model produces reliable predictions of delay and therefore the methodology can be applied to early stage planning and design optimization for communication links. Moreover, as a byproduct of this work, we also present in this paper an interesting phenomenon which we term "interconnection fringing". The fringing effect is attributed to the competition for routing resources in a communication link and will lengthen interconnections and, therefore, increase the delay.
Mak T, D'Alessandro C, Sedcole P, et al., 2008, Implementation of Wave-Pipelined Interconnects in FPGAs, Publisher: IEEE, Pages: 213-214
Global interconnection and communication at high clock frequencies are becoming more problematic in FPGA. In this paper, we address this problem by presenting an interconnect wave-pipelining strategy, which utilizes the existing programmable interconnects fabrics to provide high-throughput communication in FPGA. Two design approaches for interconnect wave-pipelining, using simple clock phase shifting and asynchronous phase encoding, are presented in this paper. Experimental results from a Xilinx Virtex-5 FPGA device are also presented.
Clarke JA, Constantinides GA, Cheung PYK, 2008, Glitch-Aware Output Switching Activity from Word-Level Statistics, Proc. IEEE International Symposium on Circuits and Systems, Pages: 1792-1795
Angelopoulou ME, Cheung PYK, Masselos K, et al., 2008, Implementation and comparison of the 5/3 lifting 2D discrete wavelet transform computation schedules on FPGAs, 5th IEEE International Conference on Field Programmable Technology, Publisher: SPRINGER, Pages: 3-21, ISSN: 1939-8018
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- Citations: 30
Angelopoulou M, Bouganis C, Cheung PYK, et al., 2008, FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor, Pages: 125-136
Cope BT, Cheung PYK, Luk W, 2008, Using Reconfigurable Logic to Optimise GPU Memory Accesses, Pages: 44-49
Angelopoulou ME, Bouganis C-S, Cheung PYK, 2008, VIDEO ENHANCEMENT ON AN ADAPTIVE IMAGE SENSOR, 15th IEEE International Conference on Image Processing (ICIP 2008), Publisher: IEEE, Pages: 685-688, ISSN: 1522-4880
Cope B, Cheung PYK, Luke W, 2008, Systematic Design Space Exploration for Customisable Multi-Processor Architectures, International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation, Publisher: IEEE, Pages: 57-+
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- Citations: 2
Becker T, Jamieson P, Luk W, et al., 2008, TOWARDS BENCHMARKING ENERGY EFFICIENCY OF RECONFIGURABLE ARCHITECTURES, 18th International Conference on Field Programmable and Logic Applications, Publisher: IEEE, Pages: 690-+, ISSN: 1946-1488
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- Citations: 1
Cope B, Cheung PYK, Luk W, 2008, Using reconfigurable logic to optimise GPU memory accesses, Design, Automation and Test in Europe Conference and Exhibition (DATE 08), Publisher: IEEE, Pages: 42-+, ISSN: 1530-1591
Ang SS, Constantinides GA, Luk W, et al., 2008, Custom parallel caching schemes for hardware-accelerated image compression, JOURNAL OF REAL-TIME IMAGE PROCESSING, Vol: 3, Pages: 289-302
In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on field programmable gate arrays (FPGAs) is becoming increasingly desirable, because of the computational parallelism on these platforms as well as the measure of flexibility afforded to designers. Typically, video data are stored in large and slow external memory arrays, but the impact of the memory access bottleneck may be reduced by buffering frequently used data in fast on-chip memories. The order of the memory accesses, resulting from many compression algorithms are dependent on the input data (Jain in Proceedings of the IEEE, pp. 349–389, 1981). These data-dependent memory accesses complicate the exploitation of data re-use, and subsequently reduce the extent to which an application may be accelerated. In this paper, we present a hybrid memory sub-system which is able to capture data re-use effectively in spite of data-dependent memory accesses. This memory sub-system is made up of a custom parallel cache and a scratchpad memory. Further, the framework is capable of exploiting 2D spatial locality, which is frequently exhibited in the access patterns of image processing applications. In a case study involving the quad-tree structured pulse code modulation (QSDPCM) application, the impact of data dependence on memory accesses is shown to be significant. In comparison with an implementation which only employs an SPM, performance improvements of up to 1.7× and 1.4× are observed through actual implementation on two modern FPGA platforms. These performance improvements are more pronounced for image sequences exhibiting greater inter-frame movements. In addition, reductions of on-chip memory resources by up to 3.2× are achievable using this framework. These results indicate that, on custom hardware platforms, there is substantial scope for improvement in the capture of data re-us
Angelopoulou M, Bouganis C, Cheung PYK, 2008, Video Enhancement on an Adaptive Image Sensor, Pages: 681-684
Liu Y, Bouganis C, Cheung PYK, 2008, Real-Time Spatiotemporal Saliency, Next generation artificial vision systems, Editors: Bharath, Petrou, Publisher: Artech House Publishers, ISBN: 9781596932241
Mak T, D'Alessandro C, Sedcole P, et al., 2008, Global Interconnections in FPGAs: Modeling and Performance Analysis, ACM International Workshop on System Level Interconnect Prediction, Publisher: ASSOC COMPUTING MACHINERY, Pages: 51-58
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- Citations: 4
Angelopoulou M, Bouganis C, Cheung PYK, et al., 2008, FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor, Pages: 125-136
Wong JSJ, Sedcole P, Cheung PYK, 2008, A Transition Probability Based Delay Measurement Method for Arbitrary Circuits on FPGAs, International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 105-112
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- Citations: 11
Wong JSJ, Cheung PYK, Sedcole P, 2008, COMBATING PROCESS VARIATION ON FPGAS WITH A PRECISE AT-SPEED DELAY MEASUREMENT METHOD, 18th International Conference on Field Programmable and Logic Applications, Publisher: IEEE, Pages: 702-703, ISSN: 1946-1488
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- Citations: 1
Sedcole P, Wong JS, Cheung PYK, 2008, Modelling and Compensating for Clock Skew Variability in FPGAs, International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 217-224
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- Citations: 4
Mak T, Sedcole P, Cheung PYK, et al., 2008, Wave-Pipelined Signaling for On-FPGA Communication, International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 9-+
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- Citations: 3
Turkington KJ, Constantinides GA, Masselos K, et al., 2008, Co-optimisation of Datapath and Memory in Outer Loop Pipelining, Pages: 1-8
Liu Q, Constantinides GA, Masselos K, et al., 2008, Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework, Pages: 179-184
Mak T, Sedcole P, Cheung PYK, et al., 2008, Interconnection Lengths and Delays Estimation for Communication Links in FPGAs, ACM International Workshop on System Level Interconnect Prediction, Publisher: ASSOC COMPUTING MACHINERY, Pages: 1-9
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- Citations: 3
Stott E, Sedcole P, Cheung PYK, 2008, Fault tolerant methods for reliability in FPGAs, International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 415-420
Fahmy SA, Bouganis C, Cheung PYK, et al., 2007, Real-time hardware acceleration of the trace transform, Journal of Real-Time Image Processing, Vol: 2, Pages: 235-248, ISSN: 1861-8200
Fahmy SA, Bouganis C, Cheung PYK, et al., 2007, Real-time hardware acceleration of the trace transform, Journal of Real-Time Image Processing, Vol: 2, Pages: 235-248, ISSN: 1861-8200
Wong JSJ, Sedcole P, Cheung PYK, 2007, Self-characterization of Combinatorial Circuit Delays in FPGAs, Pages: 17-23
Sedcole P, Cheung PYK, Constantinides GA, et al., 2007, Run-Time Integration of Reconfigurable Video Processing Systems, IEEE Trans VLSI Systems, Vol: 15, Pages: 1003-1016
Mak TST, Sedcole P, Cheung PYK, et al., 2007, Average interconnection delay estimation for on-FPGA communication links, Electronics Letters, Vol: 43, Pages: 918-919
A new method is presented and an analytical expression is derived for average interconnection delay estimation. This method is directly applicable to predicting the average delay for high-bandwidth communication links implemented on FPGAs. The theoretical results are compared with the measured data from the actual circuits and an average error of 4.6% is reported.
Bouganis C, Pournara I, Cheung PYK, 2007, Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs, IEEE Symposium on Field-Programmable Custom Computing Machines, Pages: 141-150
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