Publications
349 results found
Bouganis C, Pournara I, Cheung PYK, 2007, Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs, IEEE Symposium on Field-Programmable Custom Computing Machines, Pages: 141-150
Morris GW, Constantinides GA, Cheung PYK, 2007, ROM to DSP Block Transfer for Resource Constrained Synthesis, IET Computers and Digital Techniques, Vol: 1, Pages: 17-26
Liu Y, Bouganis C-S, Cheung PYK, 2007, Efficient Mapping of a Kalman Filter into FPGA Using Tayor Expansion
Clarke JA, Constantinides GA, Cheung PYK, 2007, On the feasibility of early routing capacitance estimation for FPGAs, 17th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 234-239, ISSN: 1946-1488
- Author Web Link
- Cite
- Citations: 1
Liu Q, Constantinides GA, Masselos K, et al., 2007, Automatic On-chip Memory Minimization for Data Reuse
Mak TST, Sedcole P, Cheung PYK, et al., 2007, A hybrid analog-digital routing network for NoC dynamic routing, 1st International Symposium on Networks-on-Chip, Publisher: IEEE COMPUTER SOC, Pages: 173-+
- Author Web Link
- Cite
- Citations: 7
Sedcole P, Cheung PYK, 2007, Parametric Yield in FPGAs Due to Within-die Delay Variations: A Quantitative Analysis, 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Publisher: ASSOC COMPUTING MACHINERY, Pages: 178-187
- Author Web Link
- Cite
- Citations: 9
Arifin S, Cheung PYK, 2007, A novel probabilistic approach to modeling the pleasure-arousal-dominance content of the video based on "Working memory", International Conference on Semantic Computing (ICSC 2007), Publisher: IEEE COMPUTER SOC, Pages: 147-+
- Author Web Link
- Cite
- Citations: 11
Wong JSJ, Sedcole P, Cheung PYK, 2007, Self-characterization of combinatorial circuit delays in FPGAs, Annual International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 17-23
- Author Web Link
- Cite
- Citations: 11
Arifin S, Cheung PYK, 2007, A novel video parsing algorithm utilizing the pleasure-arousal-dominance emotional information, IEEE International Conference on Image Processing (ICIP 2007), Publisher: IEEE, Pages: 3129-3132, ISSN: 1522-4880
Becker T, Luk W, Cheung PYK, 2007, Enhancing relocatability of partial bitstreams for run-time reconfiguration, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 35-+
- Author Web Link
- Cite
- Citations: 47
Cope B, Cheung PYK, Luk W, 2007, Bridging the gap between FPGAs and multi-processor architectures: A video processing perspective, 18th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Publisher: IEEE, Pages: 308-+, ISSN: 1063-6862
- Author Web Link
- Cite
- Citations: 1
Ang S-S, Constantinides GA, Luk W, et al., 2007, A Hybrid Memory Sub-system for Video Coding Applications
Smith AM, Constantinides GA, Cheung PYK, 2007, Fused-Arithmetic Generation for Reconfigurable Devices Using Common Subgraph Extraction, Pages: 105-112
Bouganis C, Pournara I, Cheung PYK, 2006, A statistical framework for dimensionality reduction implementation in FPGAs, IEEE International Conference on Field Programmable Technology, Pages: 365-368
Bouganis C, Pournara I, Cheung PYK, 2006, A statistical framework for dimensionality reduction implementation in FPGAs, IEEE International Conference on Field Programmable Technology, Pages: 365-368
Ang S-S, Constantinides GA, Luk W, et al., 2006, The Cost of Data Dependence in Motion Vector Estimation for Reconfigurable Platforms, Pages: 333-336
Sedcole N P, Cheung, P Y K, 2006, Within-die Delay Variability in 90nm FPGAs and Beyond, Pages: 97-104
Liu Y, Bouganis C-S, Cheung, et al., 2006, A Spatiotemporal Saliency Framework, Pages: 437-440
Campregher N, Cheung, P Y K, et al., 2006, Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs, Pages: 455-460
Smith A M, Constantinides G A, Cheung, et al., 2006, A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design, Pages: 521-526
Fahmy S A, Bouganis C, Cheung, et al., 2006, Efficient Realtime FPGA Implementation of the Trace Transform, IEEE International Conference on Field-Programmable Logic, Pages: 199-204
Arifin S, Cheung, P Y K, 2006, Towards Affective Level Video Applications: A novel FPGA based video Arousal Content Modeling System, IEEE International Conference on Field-Programmable Logic
Mak S T, Sedcole N P, Cheung, et al., 2006, On-FPGA Communication Architectures and Design Factors, IEEE International Conference on Field-Programmable Logic, Pages: 161-168
Mak S T, Sedcole N P, Cheung, et al., 2006, On-FPGA Communication Architectures and Design Factors, IEEE International Conference on Field-Programmable Logic, Pages: 161-168
Bouganis C, Cheung, P Y K, et al., 2006, FPGA-accelerated pre-attentive segmentation in Primary Visual Cortex, IEEE International Conference on Field-Programmable Logic
Sidahao N, Constantinides G A, Cheung, et al., 2006, FPGA Implementation of Polyphase Filters Using MRM, Engineering Transactions: A Research Publication of Mahanakorn University of Tec, Vol: 1, Pages: 58-63
Clarke J A, Abdul Gaffar A M, Constantinides G A, et al., 2006, Fast word-level power models for synthesis of FPGA-based arithmetic, IEEE International Symposium on Circuits and Systems, Pages: 1299-1302
Smith A M, Constantinides G A, Cheung, et al., 2006, A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design, IEEE International Symposium on Field-Programmable Custom Computing Machines, Pages: 275-276
Clarke J A, Abdul Gaffar A M, Constantinides G A, et al., 2006, Fast word-level power models for synthesis of FPGA-based arithmetic, IEEE International Symposium on Circuits and Systems, Pages: 1299-1302
This data is extracted from the Web of Science and reproduced under a licence from Thomson Reuters. You may not copy or re-distribute this data in whole or in part without the written consent of the Science business of Thomson Reuters.