Publications
349 results found
Liu Y, Bouganis C, Cheung PYK, et al., 2006, Hardware Efficient Architectures for Eigenvalue Computation, Design, Automation and Test in Europe, Pages: 953-958
Campregher N, Cheung, P Y K, et al., 2006, Yield Enhancements of Design-Specific FPGAs, Pages: 93-100
Todman TJ, Constantinides GA, Wilton SJE, et al., 2006, Reconfigurable computing: Architectures and design methods, System-on-Chip: Next Generation Electronics, Pages: 451-494, ISBN: 9780863415524
This chapter surveys two aspects of reconfigurable computing: architectures and design methods. The main trends in architectures are coarse-grained fabrics, heterogeneous functions and soft cores. The main trends in design methods are special purpose design methods, low power techniques and high-level transformations. We wonder what a survey of reconfigurable computing, written in 2015, will cover?.
Todman T J, Constantinides G A, Wilton, et al., 2006, Reconfigurable Computing: Architectures and Design Methods, System-on-Chip: Next Generation Electronics, Editors: Al-Hashimi, Publisher: IEE Press
Caffarena G, Constantinides G, Cheung P, et al., 2006, Optimal Combined Word-length Allocation and Architectural Synthesis of Digital Signal Processing Circuits, IEEE Transactions on Circuits and Systems II, Vol: 53, Pages: 339-343
Sedcole P, Cheung PYK, 2006, Within-die delay variability in 90nm FPGAs and beyond, 5th IEEE International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 97-+
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- Citations: 68
Ang SS, Constantinides GA, Luk W, et al., 2006, A flexible multi-port caching scheme for reconfigurable platforms, Proc. Applied Reconfigurable Computing
Sedcole P, Cheung PYK, Constantinides GA, et al., 2006, On-Chip Communication in Run-Time Assembled Reconfigurable Systems, Pages: 168-176
Smith AM, Constantinides GA, Cheung PYK, 2006, A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design, Pages: 521-526
Liu Y, Bouganis C-S, Cheung PYK, et al., 2006, Hardware efficient architectures for eigenvalue computation, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Publisher: IEEE, Pages: 951-+, ISSN: 1530-1591
Arifin S, Cheung PYK, 2006, User attention based arousal content modeling, IEEE International Conference on Image Processing (ICIP 2006), Publisher: IEEE, Pages: 433-+, ISSN: 1522-4880
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- Citations: 6
Arifin S, Cheung PYK, 2006, A novel FPGA-based implementation of time adaptive clustering for Logical Story Unit segmentation, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Publisher: IEEE, Pages: 1562-+, ISSN: 1530-1591
Ang S-S, Constantinides GA, Luk W, et al., 2006, A Flexible Multi-Port Caching Scheme for Reconfigurable Platforms, Pages: 205-216
Todman, Constantinides GA, Wilton SJE, et al., 2006, Reconfigurable Computing: Architectures and Design Methods
Fahmy SA, Bouganis C-S, Cheung PYK, et al., 2006, Efficient realtime FPGA implementation of the Trace Transform, 16th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 555-560, ISSN: 1946-1488
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- Citations: 1
Rissa T, Cheung PYK, Luk W, 2006, System level design exploration of JPEG 2000 with SoftSONIC virtual hardware platform, 49th IEEE International Midwest Symposium on Circuits and Systems, Publisher: IEEE, Pages: 276-+, ISSN: 1548-3746
Angelopoulou M, Masselos K, Cheung P, et al., 2006, A comparison of 2-D discrete wavelet transform computation schedules on FPGAs, 5th IEEE International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 181-188
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- Citations: 7
Lee DU, Luk W, Villasenor JD, et al., 2005, The effects of polynomial degrees on the hierarchical segmentation method, New Algorithms, Architectures and Applications for Reconfigurable Computing, Pages: 301-313, ISBN: 9781402031274
This chapter presents the effects of polynomial degrees on the hierarchical segmentation method (HSM) for approximating functions. HSM uses a novel hierarchy of uniform segments and segments with size varying by powers of two. This scheme enables us to approximate non-linear regions of a function particularly well. The degrees of the polynomials play an important role when approximating functions with HSM: the higher the degree, the fewer segments are needed to meet the same error requirement. However, higher degree polynomials require more multipliers and adders, leading to higher circuit complexity and more delay. Hence, there is a tradeoff between table size, circuit complexity and delay. We explore these tradeoffs with four functions:, x log(x), a high order rational function and cos(πx/2). We present results for polynomials up to the fifth order for various operand sizes between 8 and 24 bits. © 2005 Springer.
Rissa T, Cheung PYK, Luk W, 2005, Mixed abstraction execution for the SoftSONIC virtual hardware platform, Pages: 976-979, ISSN: 1548-3746
This paper presents a systematic approach for mixed abstraction execution in the SoftSONIC virtual hardware platform. In mixed abstraction execution different levels of abstraction, for example clockless coarse granularity Transaction Level Modelling (TLM) and clocked Register Transfer Level (RTL) models can be co-simulated. When combining 10 Hz to 1 kHz-range RTL model of component under development with 100 kHz to 10 MHz-range TLM model of rest of the system, the full system simulates close to the speed of one RTL component alone. By verifying the components in full system simulation, error-prone and tedious per-component testbench generation can be avoided. Mixed abstraction execution also gives the possibility of gradual refinement and parallel development and verification of system components. These aspects can reduce the overall design time, as we show in this paper with the development of a real-time JPEG 2000 hardware encoder. © 2005 IEEE.
Cheung RCC, Telle NJB, Luk W, et al., 2005, Customizable elliptic curve cryptosystems, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol: 13, Pages: 1048-1059, ISSN: 1063-8210
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- Citations: 41
Fahmy SA, Cheung PYK, Luk W, 2005, Novel FPGA-based implementation of median and weighted median filters for image processing, Proceedings of IEEE International Conference on Field Programmable Logic (FPL'05), Publisher: Institute of Electrical Engineers, Pages: 142-147
Bouganis C-S, Cheung, P Y K, et al., 2005, Heterogeneity Exploration for Multiple 2D Filter Designs, Pages: 263-268
Wiangtong T, Cheung PYK, Luk W, 2005, Hardware/software Codesign for Data-dominated DSP Applications, IEEE Signal Processing Magazine, Vol: 22, Pages: 14-22
Theerayod WT, Cheung PYK, Luk W, 2005, Hardware/software codesign, IEEE SIGNAL PROCESSING MAGAZINE, Vol: 22, Pages: 14-22, ISSN: 1053-5888
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- Citations: 1
Constantinides GA, Cheung PYK, Luk W, 2005, Optimum and Heuristic Synthesis of Multiple Word-length Architectures, IEEE Transactions on Very Large Scale Integration Systems, Vol: 13, Pages: 39-57
Sidahao N, Constantinides GA, Cheung PYK, 2005, A Heuristic approach for multiple restricted multiplication, New York, IEEE international symposium on circuits and systems (iscas), Kobe, Japan, 23 - 26 2005, Publisher: IEEE, Pages: 692-695
Melis WJC, Turkington K, Whitton A, et al., 2005, Cell based motion estimators for reconfigurable platforms, Athens, International conference on engineering of reconfigurable systems and algorithms, 27 - 30 June 2005, Las Vegas, NV, Publisher: C S R e A Press, Pages: 218-224
Luk W, Cheung PYK, Shirazi N, 2005, Configurable Computing, ELECTRICAL ENGINEERING HANDBOOK, Editors: Chen, Publisher: ELSEVIER SCIENCE BV, Pages: 343-354, ISBN: 978-0-12-170960-0
Campregher N, Cheung PYK, Constantinides GA, et al., 2005, Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs, New York, NY, FPGA '05: proceedings of the 2005 ACM/SIGDA 13th international symposium on field-programmable gate arrays, Monterey, California, USA, 20 - 22 February 2005, Publisher: ACM Press, Pages: 138-148
Bouganis C-S, Constantinides GA, Cheung PYK, 2005, A Novel 2D Filter Design Methodology for Heterogeneous Devices, Pages: 13-22
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