Imperial College London
Alternate

Professor Peter Y. K. Cheung

Faculty of Engineering, Dyson School of Design Engineering

Professor of Digital Systems
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Davis:2016:10.1145/2847263.2847316,
author = {Davis, JJ and Hung, E and Levine, J and Stott, E and Cheung, PYK and Constantinides, GA},
doi = {10.1145/2847263.2847316},
pages = {276--276},
publisher = {ACM},
title = {Knowledge is Power: Module-level Sensing for Runtime Optimisation},
url = {http://dx.doi.org/10.1145/2847263.2847316},
year = {2016}
}
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RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - We propose the compile-time instrumentation of coexisting modules---IP blocks, accelerators, etc.---implemented in FPGAs. The efficient mapping of tasks to execution units can then be achieved, for power and/or timing performance, by tracking dynamic power consumption and/or timing slack online at module-level granularity. Our proposed instrumentation is transparent, thereby not affecting circuit functionality. Power and timing overheads have proven to be small and tend to be outweighed by the exposed runtime benefits.
AU  - Davis,JJ
AU  - Hung,E
AU  - Levine,J
AU  - Stott,E
AU  - Cheung,PYK
AU  - Constantinides,GA
DO  - 10.1145/2847263.2847316
EP  - 276
PB  - ACM
PY  - 2016///
SP  - 276
TI  - Knowledge is Power: Module-level Sensing for Runtime Optimisation
UR  - http://dx.doi.org/10.1145/2847263.2847316
UR  - http://dl.acm.org/citation.cfm?doid=2847263.2847316
UR  - http://hdl.handle.net/10044/1/31179
ER  -
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