Professor Peter Y. K. Cheung

Faculty of Engineering, Dyson School of Design Engineering

Professor of Digital Systems

Contact

+44 (0)20 7594 6200p.cheung Website

Assistant

Mrs Wiesia Hsissen +44 (0)20 7594 6261

Location

910BElectrical EngineeringSouth Kensington Campus

Summary

Publications

Citation

BibTex format

@inproceedings{Stott:2014:10.1109/FCCM.2014.32,
author = {Stott, E and Levine, JM and Cheung, PYK and Kapre, N},
doi = {10.1109/FCCM.2014.32},
pages = {96--99},
publisher = {IEEE},
title = {Timing Fault Detection in FPGA-based Circuits},
url = {http://dx.doi.org/10.1109/FCCM.2014.32},
year = {2014}
}

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RIS format (EndNote, RefMan)

TY  - CPAPER
AU  - Stott,E
AU  - Levine,JM
AU  - Cheung,PYK
AU  - Kapre,N
DO  - 10.1109/FCCM.2014.32
EP  - 99
PB  - IEEE
PY  - 2014///
SP  - 96
TI  - Timing Fault Detection in FPGA-based Circuits
UR  - http://dx.doi.org/10.1109/FCCM.2014.32
UR  - https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000410585800022&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=a2bf6146997ec60c407a63945d4e92bb
ER  -

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