155 results found
Bolten M, Franchetti F, Kelly PHJ, et al., 2017, Algebraic description and automatic generation of multigrid methods in SPIRAL, CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, Vol: 29, ISSN: 1532-0626
Luporini F, Ham DA, Kelly PHJ, 2017, An Algorithm for the Optimization of Finite Element Integration Loops, ACM TRANSACTIONS ON MATHEMATICAL SOFTWARE, Vol: 44, ISSN: 0098-3500
Nardi L, Bodin B, Saeedi S, et al., 2017, Algorithmic performance-accuracy trade-off in 3D vision applications using HyperMapper, Pages: 1434-1443
© 2017 IEEE. In this paper we investigate an emerging application, 3D scene understanding, likely to be significant in the mobile space in the near future. The goal of this exploration is to reduce execution time while meeting our quality of result objectives. In previous work, we showed for the first time that it is possible to map this application to power constrained embedded systems, highlighting that decision choices made at the algorithmic design-level have the most significant impact. As the algorithmic design space is too large to be exhaustively evaluated, we use a previously introduced multi-objective random forest active learning prediction framework dubbed HyperMapper, to find good algorithmic designs. We show that HyperMapper generalizes on a recent cutting edge 3D scene understanding algorithm and on a modern GPU-based computer architecture. HyperMapper is able to beat an expert human hand-tuning the algorithmic parameters of the class of computer vision applications taken under consideration in this paper automatically. In addition, we use crowd-sourcing using a 3D scene understanding Android app to show that the Pareto front obtained on an embedded system can be used to accelerate the same application on all the 83 smart-phones and tablets with speedups ranging from 2x to over 12x.
Rathgeber F, Ham DA, Mitchell L, et al., 2017, Firedrake: Automating the Finite Element Method by Composing Abstractions, ACM TRANSACTIONS ON MATHEMATICAL SOFTWARE, Vol: 43, ISSN: 0098-3500
Saeedi S, Nardi L, Johns E, et al., 2017, Application-oriented design space exploration for SLAM algorithms, Pages: 5716-5723, ISSN: 1050-4729
© 2017 IEEE. In visual SLAM, there are many software and hardware parameters, such as algorithmic thresholds and GPU frequency, that need to be tuned; however, this tuning should also take into account the structure and motion of the camera. In this paper, we determine the complexity of the structure and motion with a few parameters calculated using information theory. Depending on this complexity and the desired performance metrics, suitable parameters are explored and determined. Additionally, based on the proposed structure and motion parameters, several applications are presented, including a novel active SLAM approach which guides the camera in such a way that the SLAM algorithm achieves the desired performance metrics. Real-world and simulated experimental results demonstrate the effectiveness of the proposed design space and its applications.
Unat D, Dubey A, Hoefler T, et al., 2017, Trends in Data Locality Abstractions for HPC Systems, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, Vol: 28, Pages: 3007-3020, ISSN: 1045-9219
Bercea G-T, McRae ATT, Ham DA, et al., 2016, A structure-exploiting numbering algorithm for finite elements on extruded meshes, and its performance evaluation in Firedrake, GEOSCIENTIFIC MODEL DEVELOPMENT, Vol: 9, Pages: 3803-3815, ISSN: 1991-959X
Bodin B, Nardi L, Kelly PHJ, et al., 2016, Diplomat: Mapping of Multi-kernel Applications Using a Static Dataflow Abstraction, 24th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), Publisher: IEEE, Pages: 241-250, ISSN: 1526-7539
Bodin B, Nardi L, Zia MZ, et al., 2016, Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding, International conference on Parallel Architectures and Compilation Techniques, Publisher: IEEE
System designers typically use well-studied benchmarks toevaluate and improve new architectures and compilers. Wedesign tomorrow's systems based on yesterday's applications.In this paper we investigate an emerging application,3D scene understanding, likely to be signi cant in the mobilespace in the near future. Until now, this application couldonly run in real-time on desktop GPUs. In this work, weexamine how it can be mapped to power constrained embeddedsystems. Key to our approach is the idea of incrementalco-design exploration, where optimization choices that concernthe domain layer are incrementally explored togetherwith low-level compiler and architecture choices. The goalof this exploration is to reduce execution time while minimizingpower and meeting our quality of result objective.As the design space is too large to exhaustively evaluate,we use active learning based on a random forest predictorto nd good designs. We show that our approach can, forthe rst time, achieve dense 3D mapping and tracking in thereal-time range within a 1W power budget on a popular embeddeddevice. This is a 4.8x execution time improvementand a 2.8x power reduction compared to the state-of-the-art.
Reguly IZ, Mudalige GR, Bertolli C, et al., 2016, Acceleration of a Full-Scale Industrial CFD Application with OP2, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, Vol: 27, Pages: 1265-1278, ISSN: 1045-9219
Wozniak BD, Witherden FD, Russell FP, et al., 2016, GiMMiK-Generating bespoke matrix multiplication kernels for accelerators: Application to high-order Computational Fluid Dynamics, COMPUTER PHYSICS COMMUNICATIONS, Vol: 202, Pages: 12-22, ISSN: 0010-4655
Zia MZ, Nardi L, Jack A, et al., 2016, Comparative Design Space Exploration of Dense and Semi-Dense SLAM, IEEE International Conference on Robotics and Automation (ICRA), Publisher: IEEE, Pages: 1292-1299, ISSN: 1050-4729
Nardi L, Bodin B, Zia MZ, et al., 2015, Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM., Publisher: IEEE, Pages: 5783-5790
Nardi L, Bodin B, Zia MZ, et al., 2015, Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM, IEEE International Conference on Robotics and Automation (ICRA), Publisher: IEEE COMPUTER SOC, Pages: 5783-5790, ISSN: 1050-4729
Popovici DT, Russell FP, Wilkinson K, et al., 2015, Generating Optimized Fourier Interpolation Routines for Density Functional Theory using SPIRAL, 29th IEEE International Parallel and Distributed Processing Symposium (IPDPS), Publisher: IEEE, Pages: 743-752, ISSN: 1530-2075
Rokos G, Gorman G, Kelly PHJ, 2015, A Fast and Scalable Graph Coloring Algorithm for Multi-core and Many-core Architectures, 21st International Conference on Parallel and Distributed Computing (Euro-Par), Publisher: SPRINGER-VERLAG BERLIN, Pages: 414-425, ISSN: 0302-9743
Russell FP, Wilkinson KA, Kelly PHJ, et al., 2015, Optimised three-dimensional Fourier interpolation: An analysis of techniques and application to a linear-scaling density functional theory code, COMPUTER PHYSICS COMMUNICATIONS, Vol: 187, Pages: 8-19, ISSN: 0010-4655
Collingbourne P, Cadar C, Kelly PHJ, 2014, Symbolic Crosschecking of Data-Parallel Floating-Point Code, IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, Vol: 40, Pages: 710-737, ISSN: 0098-5589
Konstantinidis A, Kelly PHJ, Ramanujam J, et al., 2014, Parametric GPU Code Generation for Affine Loop Programs, 26th International Workshop on Languages and Compilers for Parallel Computing (LCPC), Publisher: SPRINGER-VERLAG BERLIN, Pages: 136-151, ISSN: 0302-9743
Luporini F, Varbanescu AL, Rathgeber F, et al., 2014, Cross-Loop Optimization of Arithmetic Intensity for Finite Element Local Assembly, ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, Vol: 11, ISSN: 1544-3566
Salas-Moreno RF, Glocker B, Kelly PHJ, et al., 2014, Dense Planar SLAM, IEEE International Symposium on Mixed and Augmented Reality (ISMAR) - Science and Technology, Publisher: IEEE, Pages: 157-164, ISSN: 1554-7868
Salas-Moreno RF, Glocker B, Kelly PHJ, et al., 2014, [DEMO] Dense Planar SLAM, IEEE International Symposium on Mixed and Augmented Reality (ISMAR) - Science and Technology, Publisher: IEEE, Pages: 367-368, ISSN: 1554-7868
Strout MM, Luporini F, Krieger CD, et al., 2014, Generalizing Run-time Tiling with the Loop Chain Abstraction, IEEE 28th International Parallel & Distributed Processing Symposium (IPDPS), Publisher: IEEE, ISSN: 1530-2075
Bertolli C, Betts A, Loriant N, et al., 2013, Compiler optimizations for industrial unstructured mesh CFD applications on GPUs, Pages: 112-126, ISSN: 0302-9743
Graphical Processing Units (GPUs) have shown acceleration factors over multicores for structured mesh-based Computational Fluid Dynamics (CFD). However, the value remains unclear for dynamic and irregular applications. Our motivating example is HYDRA, an unstructured mesh application used in production at Rolls-Royce for the simulation of turbomachinery components of jet engines. We describe three techniques for GPU optimization of unstructured mesh applications: a technique able to split a highly complex loop into simpler loops, a kernel specific alternative code synthesis, and configuration parameter tuning. Using these optimizations systematically on HYDRA improves the GPU performance relative to the multicore CPU. We show how these optimizations can be automated in a compiler, through user annotations. Performance analysis of a large number of complex loops enables us to study the relationship between optimizations and resource requirements of loops, in terms of registers and shared memory, which directly affect the loop performance. © Springer-Verlag Berlin Heidelberg 2013.
Architectural design, particularly in large scale master planning projects, has yet to fully undergo the computational revolution experienced by other design-led industries such as automotive and aerospace. These industries use computational frameworks to undertake automated design analysis and design space exploration. However, within the Architectural, Engineering and Construction (AEC) industries wend no such computational platforms. This precludes the rapid analysis needed for quantitative design iteration which is required for sustainable design. This is a current computing frontier. This paper considers the computational solutions to the challenges preventing such advances to improve architectural design performance for a more sustainable future. We present a practical discussion of the computational challenges and opportunities in this industry and present a computational framework "HierSynth" with a data model designed to the needs of this industry. We report the results and lessons learned from applying this framework to a major commercial urban master planning project. This framework was used to automate and augment existing practice and was used to undertake previously infeasible, designer lead, design space exploration. During the casestudy an order of magnitude more analysis cycles were undertaken than literature suggests is normal; each occurring in hours not days.
Birch D, Liang H, Ko J, et al., 2013, Multidisciplinary Engineering Models: Methodology and Case Study in Spreadsheet Analytics, European Spreadsheet Risks Interest Group 14th Annual Conference (EuSpRIG 2013), Publisher: EuSpRIG, Pages: 1-12
Chong N, Donaldson AF, Kelly PHJ, et al., 2013, Barrier Invariants: A Shared State Abstraction for the Analysis of Data-Dependent GPU Kernels, 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications (OOPSLA'13), Publisher: ASSOC COMPUTING MACHINERY, Pages: 605-621, ISSN: 0362-1340
Grosser T, Cohen A, Kelly PHJ, et al., 2013, Split tiling for GPUs: Automatic parallelization using trapezoidal tiles, Pages: 24-31
Tiling is a key technique to enhance data reuse. For computations structured as one sequential outer "time" loop enclosing a set of parallel inner loops, tiling only the parallel inner loops may not enable enough data reuse in the cache. Tiling the inner loops along with the outer time loop enhances data locality but may require other transformations like loop skewing that inhibit inter-tile parallelism. One approach to tiling that enhances data locality without inhibiting inter-tile parallelism is split tiling, where tiles are subdivided into a sequence of trapezoidal computation steps. In this paper, we develop an approach to generate split tiled code for GPUs in the PPCG polyhedral code generator. We propose a generic algorithm to calculate index-set splitting that enables us to perform tiling for locality and synchronization avoidance, while simultaneously maintaining parallelism, without the need for skewing or redundant computations. Our algorithm performs split tiling for an arbitrary number of dimensions and without the need to construct any large integer linear program. The method and its implementation are evaluated on standard stencil kernels and compared with a state-of-the-art polyhedral compiler and with a domain-specific stencil compiler, both targeting CUDA GPUs. Copyright 2013 ACM.
Kelly PH, 2013, Split Tiling for GPUs: Automatic Parallelization Using Trapezoidal Tiles, 6th Workshop on General Purpose Processor Using Graphics Processing Units, Publisher: ACM Press
Tiling is a key technique to enhance data reuse. For computations structured as one sequential outer "time" loop enclosing a set of parallel inner loops, tiling only the parallel inner loops may not enable enough data reuse in the cache. Tiling the inner loops along with the outer time loop enhances data locality but may require other transformations like loop skewing that inhibit inter-tile parallelism.One approach to tiling that enhances data locality without inhibiting inter-tile parallelism is split tiling, where tiles are subdivided into a sequence of trapezoidal computation steps. In this paper, we develop an approach to generate split tiled code for GPUs in the PPCG polyhedral code generator. We propose a generic algorithm to calculate index-set splitting that enables us to perform tiling for locality and synchronization avoidance, while simultaneously maintaining parallelism, without the need for skewing or redundant computations. Our algorithm performs split tiling for an arbitrary number of dimensions and without the need to construct any large integer linear program. The method and its implementation are evaluated on standard stencil kernels and compared with a state-of-the-art polyhedral compiler and with a domain-specific stencil compiler, both targeting CUDA GPUs.
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