166 results found
Ahmadi N, Constandinou TG, Bouganis C, 2018, Spike rate estimation using Bayesian Adaptive Kernel Smoother (BAKS) and its application to brain machine interfaces, 40th International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Publisher: IEEE
Brain Machine Interfaces (BMIs) mostly utilise spike rate as an input feature for decoding a desired motor output as it conveys a useful measure to the underlying neuronal activity. The spike rate is typically estimated by a using non-overlap binning method that yields a coarse estimate. There exist several methods that can produce a smooth estimate which could potentially improve the decoding performance. However, these methods are relatively computationally heavy for real-time BMIs. To address this issue, we propose a new method for estimating spike rate that is able to yield a smooth estimate and also amenable to real-time BMIs. The proposed method, referred to as Bayesian adaptive kernel smoother (BAKS), employs kernel smoothing technique that considers the bandwidth as a random variable with prior distribution which is adaptively updated through a Bayesian framework. With appropriate selection of prior distribution and kernel function, an analytical expression can be achieved for the kernel bandwidth. We apply BAKS and evaluate its impact on of fline BMI decoding performance using Kalman filter. The results show that overlap BAKS improved the decoding performance up to 3.33% and 12.93% compared to overlap and non-overlapbinning methods, respectively, depending on the window size. This suggests the feasibility and the potential use of BAKS method for real-time BMIs.
De Marcellis A, Di Patrizio Stanchieri G, Palange E, et al., 2018, An Ultra-Wideband-Inspired System-on-Chip for an Optical Bidirectional Transcutaneous Biotelemetry, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4
Feng P, Constandinou TG, 2018, Robust Wireless Power Transfer to Multiple mm-Scale Freely-Positioned Neural Implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4
Feng P, Yeon P, Cheng Y, et al., 2018, Chip-scale coils for millimeter-sized bio-implants, IEEE Transactions on Biomedical Circuits and Systems, Pages: 1-12, ISSN: 1932-4545
Next generation implantable neural interfaces are targeting devices with mm-scale form factors that are freely floating and completely wireless. Scalability to more recording (or stimulation) channels will be achieved through distributing multiple devices, instead of the current approach that uses a single centralized implant wired to individual electrodes or arrays. In this way, challenges associated with tethers, micromotion and reliability of wiring is mitigated. This concept is now being applied to both central and peripheral nervous system interfaces. One key requirement, however, is to maximize SAR-constrained achievable wireless power transfer efficiency (PTE) of these inductive links with mm-sized receivers. Chip-scale coil structures for microsystem integration that can provide efficient near-field coupling are investigated. We develop near-optimal geometries for three specific coil structures: “in-CMOS”, “above-CMOS” (planar coil post-fabricated on a substrate) and “around-CMOS” (helical wirewound coil around substrate). We develop analytical and simulation models that have been validated in air and biological tissues by fabrications and experimentally measurements. Specifically, we prototype structures that are constrained to a 4mm x 4mm silicon substrate i.e. the planar in-/above-CMOS coils have outer diameter <4mm, whereas the around-CMOS coil has inner diameter of 4mm. The in-CMOS and above-CMOS coils have metal film thicknesses of 3μm aluminium and 25μm gold, respectively, whereas the around-CMOS coil is fabricated by winding a 25μm gold bonding-wire around the substrate. The measured quality factors (Q) of the mm-scale Rx coils are 10.5 @450.3MHz (in-CMOS), 24.61 @85MHz (above-CMOS), and 26.23 @283MHz (around-CMOS). Also, PTE of 2-coil links based on three types of chip-scale coils is measured in air and tissue environment to demonstrate tissue loss for bio-implants. The SAR-constrained maximum PTE are
Haci D, Liu Y, Ghoreishizadeh S, et al., 2018, Design Considerations for Ground Referencing in Multi-Module Neural Implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4
Haci D, Liu Y, Nikolic K, et al., 2018, Thermally Controlled Lab-on-PCB for Biomedical Applications, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4
Lauteslager T, Tommer M, Lande TS, et al., 2018, Cross-Body UWB Radar Sensing of Arterial Pulse Propagation and Ventricular Dynamics, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4
Leene L, Constandinou TG, 2018, Direct Digital Wavelet Synthesis for Embedded Biomedical Microsystems, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4
Leene L, Maslik M, Feng P, et al., 2018, Autonomous SoC for neural local field potential recording in mm-scale wireless implants, IEEE International Symposium on Circuits and Systems, Publisher: IEEE, Pages: 1-5, ISSN: 2379-447X
Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency when observing neural activity over a long period of time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing local field potentials (LFPs) only, chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a ΔΣ based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 μm CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.77μVrms. The resulting electronics has a core area of 2.1 mm2 and a power budget of 92 μW
Leene LB, Constandinou TG, 2018, A 0.006 mm<sup>2</sup>1.2 μ W Analog-to-Time Converter for Asynchronous Bio-Sensors, IEEE Journal of Solid-State Circuits, Vol: 53, Pages: 2604-2613, ISSN: 0018-9200
© 1966-2012 IEEE. This paper presents a low-power analog-to-time converter (ATC) for integrated bio-sensors. The proposed circuit facilitates the direct conversion of electrode bio-potential recordings into time-encoded digital pulses with high efficiency without prior signal amplification. This approach reduces the circuit complexity for multi-channel instrumentation systems and allows asynchronous digital control to maximize the potential power savings during sensor inactivity. A prototype fabricated using a 65-nm CMOS technology is demonstrated with measured characteristics. Experimental results show an input-referred noise figure of 3.8 μ Vrms for a 11-kHz signal bandwidth while dissipating 1.2 μ W from a 0.5-V supply and occupying 60× 80 μ m2 silicon area. This compact configuration is enabled by the proposed asynchronous readout that shapes the mismatch components arising from the multi-bit quantizer and the use of capacitive feedback.
Liu Y, Pereira J, Constandinou TG, 2018, Event-driven processing for hardware-efficient neural spike sorting, Journal of Neural Engineering, Vol: 15, Pages: 1-14, ISSN: 1741-2552
Objective. The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing. Approach. (1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability. Main results. It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources. Significance. By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.
Luan S, Williams I, Maslik M, et al., 2018, Compact standalone platform for neural recording with real-time spike sorting and data logging., J Neural Eng, Vol: 15
OBJECTIVE: Longitudinal observation of single unit neural activity from large numbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective brain-machine interfaces (BMIs). These recordings generate enormous amounts of data for transmission and storage, and typically require offline processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: (1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); (2) producing real-time, low-latency, spike sorted data; and (3) long term untethered operation. APPROACH: We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. MAIN RESULTS: The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 h at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24 h initial recording in a non-human primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. SIGNIFICANCE: The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals-revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and verifiable outp
Maslik M, Lande TS, Constandinou TG, 2018, A Clockless Method of Flicker Noise Suppression in Continuous-Time Acquisition of Biosignals, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4
Maslik M, Liu Y, Lande TS, et al., 2018, Continuous-Time Acquisition of Biosignals Using a Charge-Based ADC Topology, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, Vol: 12, Pages: 471-482, ISSN: 1932-4545
Mazza F, Liu Y, Donaldson N, et al., 2018, Integrated Devices for Micro-Package Integrity Monitoring in mm-Scale Neural Implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4
Moly A, Luan S, Zoltan M, et al., 2018, Embedded Phase-Amplitude Coupling Based Closed-Loop Platform for Parkinson's Disease, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4
Ramezani R, Liu Y, Dehkhoda F, et al., 2018, On-Probe Neural Interface ASIC for Combined Electrical Recording and Optogenetic Stimulation, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, Vol: 12, Pages: 576-588, ISSN: 1932-4545
Rapeaux A, Brunton E, Nazarpour K, et al., 2018, Preliminary study of time to recovery of rat sciatic nerve from high frequency alternating current nerve block, 40th International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Publisher: IEEE
High-Frequency alternating current nerve block has great potential for neuromodulation-based therapies. However, no precise measurements have been made of the time needed for nerves to recover from block once the signal has been turned off. This study aims to characterise time to recoveryof the rat sciatic nerve after 30 seconds of block at varying amplitudes and frequencies. Experiments were carried out in-vivo to quantify recovery times and recovery completeness within 0.7s from the end of block. The sciatic nerve was blocked with an alternating square wave signal of amplitudeand frequency ranging from 2 to 9mA and 10 to 50 kHz respectively. To determine the recovery dynamics the nerve was stimulated at 100 Hz after cessation of the blocking stimulus. Electromyogram signals were measured from the gastrocnemius medialis and tibialis anterior muscles during trials as indicators of nerve function. This allowed for nerve recovery to bemeasured with a resolution of 10 ms. This resolution is much greater than previous measurements of nerve recovery in the literature. Times for the nerve to recover to a steady state of activity ranged from 20 to 430 milliseconds and final relative recovery activity at 0.7 seconds spanned 0.2 to 1 approximately. Higher blocking signal amplitudes increased recovery time and decreased recovery completeness. These results suggestthat blocking signal properties affect nerve recovery dynamics, which could help improve neuromodulation therapies and allow more precise comparison of results across studies using different blocking signal parameters.
Szostak KM, Constandinou TG, 2018, Hermetic packaging for implantable microsystems: effectiveness of sequentially electroplated AuSn alloy, 40th International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Publisher: IEEE
With modern microtechnology, there is an aggressive miniaturization of smart devices, despite an increasing level of integration and overall complexity. It is therefore becoming increasingly important to be achieve reliable, compact packaging. For implantable medical devices (IMDs), the package must additionally provide a high quality hermetic environmentto protect the device from the human body. For chip-scale devices, AuSn eutectic bonding offers the possibility of forming compact seals that achieve ultra-low permeability. A key feature is this can be achieved at process temperatures of below 350 C, therefore allowing for the integration of sensors and microsystems with CMOS electronics within a single package. Issueshowever such as solder wetting, void formation and controlling composition make formation of high-quality repeatable seals highly challenging. Towards this aim, this paper presents our experimental work characterizing the eutectic stack deposition. We detail our design methods and process flow, share our experiences in controlling electrochemical deposition of AuSnalloy and finally discuss usability of sequential electroplating process for the formation of hermetic eutectic bonds.
Troiani F, Nikolic K, Constandinou TG, 2018, Simulating optical coherence tomography for observing nerve activity: a finite difference time domain bi-dimensional model, PLoS ONE, Vol: 13, Pages: 1-14, ISSN: 1932-6203
We present a finite difference time domain (FDTD) model for computation of A line scans in time domain optical coherence tomography (OCT). The OCT output signal is created using two different simulations for the reference and sample arms, with a successive computation of the interference signal with external software. In this paper we present the model applied to two different samples: a glass rod filled with water-sucrose solution at different concentrations and a peripheral nerve. This work aims to understand to what extent time domain OCT can be used for non-invasive, direct optical monitoring of peripheral nerve activity.
Williams I, Leene L, Constandinou TG, 2018, Next Generation Neural Interface Electronics, Circuit Design Considerations for Implantable Devices, Editors: Cong, Publisher: River Publishers, Pages: 141-178, ISBN: 978-87-93519-86-2
Williams I, Rapeaux A, Luan S, et al., 2018, Waveform Generator
Constandinou TG, Jackson A, 2017, Implantable Neural Interface
A neural interface arrangement comprising: a plurality of probes for subdural implantation into or onto a human brain, each probe including at least one sensing electrode, a coil for receiving power via inductive coupling, signal processing circuitry coupled to the sensing electrode(s), and means for wirelessly transmitting data-carrying signals arising from the sensing electrode(s); an array of coils for implantation above the dura, beneath the skull, the array of coils being for inductively coupling with the coil of each of the plurality of probes, for transmitting power to the probes; and a primary (e.g. subcutaneous) coil connected to the array of coils, the primary coil being for inductively coupling with an external transmitter device, for receiving power from the external transmitter device; wherein, in use, the primary coil is operable to receive power from the external transmitter device by inductive coupling and to cause the array of coils to transmit power to the plurality of probes by inductive coupling; and wherein, in use, the plurality of probes are operable to wirelessly transmit data-carrying signals arising from the sensing electrodes.
Davila-Montero S, Barsakcioglu DY, Jackson A, et al., 2017, Real-time Clustering Algorithm that Adapts to Dynamic Changes in Neural Recordings, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 690-693, ISSN: 0271-4302
De Marcellis A, Palange E, Faccio M, et al., 2017, A 250Mbps 24pJ/bit UWB-inspired Optical Communication System for Bioimplants, Turin, Italy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 132-135
Feng P, Constandinou TG, Yeon P, et al., 2017, Millimeter-Scale Integrated and Wirewound Coils for Powering Implantable Neural Microsystems, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 488-491
Gao C, Ghoreishizadeh S, Liu Y, et al., 2017, On-chip ID Generation for Multi-node Implantable Devices using SA-PUF, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681, ISSN: 0271-4302
Ghoreishizadeh S, Constandinou TG, 2017, On-chip Random ID Generation
Ghoreishizadeh S, Haci D, Liu Y, et al., 2017, Four-Wire Interface ASIC for a Multi-Implant Link, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Pages: 3056-3067, ISSN: 1549-8328
This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical ‘optrodes’ that facilitate a bidirectional neural interface (electrical recording, optical stimulation), and chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate(up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) which is superimposed on a power carrier. On-chip power management provides an unregulated 5V DC supply with up to 2.5mA output current for stimulation, and two regulated voltages (3.3V and 3V) with 60 dB PSRR for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35 um CMOS technology, occupying 1.5mm2 silicon area,and consumes a quiescent current of 91.2u A. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.
Ghoreishizadeh SS, Haci D, Liu Y, et al., 2017, A 4-Wire Interface SoC for Shared Multi- Implant Power Transfer and Full-duplex Communication, 8th IEEE Latin American Symposium on Circuits & Systems (LASCAS), Publisher: IEEE
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