154 results found
Liu Y, Pereira J, Constandinou TG, 2018, Event-driven processing for hardware-efficient neural spike sorting, Journal of Neural Engineering, Vol: 15, Pages: 1-14, ISSN: 1741-2552
Objective. The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing. Approach. (1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability. Main results. It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources. Significance. By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.
Luan S, Williams I, Maslik M, et al., 2018, Compact standalone platform for neural recording with real-time spike sorting and data logging., J Neural Eng, Vol: 15
OBJECTIVE: Longitudinal observation of single unit neural activity from large numbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective brain-machine interfaces (BMIs). These recordings generate enormous amounts of data for transmission and storage, and typically require offline processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: (1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); (2) producing real-time, low-latency, spike sorted data; and (3) long term untethered operation. APPROACH: We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. MAIN RESULTS: The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 h at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24 h initial recording in a non-human primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. SIGNIFICANCE: The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals-revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and verifiable outp
Maslik M, Liu Y, Lande TS, et al., 2018, Continuous-time acquisition of biosignals using a charge-based ADC topology, IEEE Transactions on Biomedical Circuits and Systems, Vol: 12, Pages: 471-482, ISSN: 1932-4545
This paper investigates Continuous-Time (CT) signal acquisition as an activity-dependent and non-uniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by non-uniform quantisation to commonly recorded biological signal fragmentsallowing a compression ratio of 5 and 26 when applied to Electrocardiogram (ECG) and Extracellular Action Potential (EAP) signals respectively. We describe several desirable properties of CT sampling including bandwidth reduction, elimination/reduction of quantisation error and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT Analogue-to-Digital Converter (CT ADC) that has been optimised for the acquisition of neural signals. This has been implemented in a commercially-available 0.35µm CMOS technology occupying a compact footprint of 0.12mm². Silicon verified measurements demonstrate an 8-bit resolution and a 4kHz bandwidth with static power consumption of 3.75µWfrom a 1.5V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39pJ energy per conversion.
Ramezani R, Liu Y, Dehkhoda F, et al., 2018, On-Probe Neural Interface ASIC for Combined Electrical Recording and Optogenetic Stimulation., IEEE Trans Biomed Circuits Syst, Vol: 12, Pages: 576-588
Neuromodulation technologies are progressing from pacemaking and sensory operations to full closed-loop control. In particular, optogenetics-the genetic modification of light sensitivity into neural tissue allows for simultaneous optical stimulation and electronic recording. This paper presents a neural interface application-specified integrated circuit (ASIC) for intelligent optoelectronic probes. The architecture is designed to enable simultaneous optical neural stimulation and electronic recording. It provides four low noise (2.08 μV) recording channels optimized for recording local field potentials (LFPs) (0.1-300 Hz bandwidth, 5 mV range, sampled 10-bit@4 kHz), which are more stable for chronic applications. For stimulation, it provides six independently addressable optical driver circuits, which can provide both intensity (8-bit resolution across a 1.1 mA range) and pulse-width modulation for high-radiance light emitting diodes (LEDs). The system includes a fully digital interface using a serial peripheral interface (SPI) protocol to allow for use with embedded controllers. The SPI interface is embedded within a finite state machine (FSM), which implements a command interpreter that can send out LFP data whilst receiving instructions to control LED emission. The circuit has been implemented in a commercially available 0.35 μm CMOS technology occupying a 1.95 mm 1.10 mm footprint for mounting onto the head of a silicon probe. Measured results are given for a variety of bench-top, in vitro and in vivo experiments, quantifying system performance and also demonstrating concurrent recording and stimulation within relevant experimental models.
Williams I, Leene L, Constandinou TG, 2018, Next Generation Neural Interface Electronics, Circuit Design Considerations for Implantable Devices, Editors: Cong, Publisher: River Publishers, Pages: 141-178, ISBN: 978-87-93519-86-2
Williams I, Rapeaux A, Luan S, et al., 2018, Waveform Generator
Constandinou TG, Jackson A, 2017, Implantable Neural Interface
A neural interface arrangement comprising: a plurality of probes for subdural implantation into or onto a human brain, each probe including at least one sensing electrode, a coil for receiving power via inductive coupling, signal processing circuitry coupled to the sensing electrode(s), and means for wirelessly transmitting data-carrying signals arising from the sensing electrode(s); an array of coils for implantation above the dura, beneath the skull, the array of coils being for inductively coupling with the coil of each of the plurality of probes, for transmitting power to the probes; and a primary (e.g. subcutaneous) coil connected to the array of coils, the primary coil being for inductively coupling with an external transmitter device, for receiving power from the external transmitter device; wherein, in use, the primary coil is operable to receive power from the external transmitter device by inductive coupling and to cause the array of coils to transmit power to the plurality of probes by inductive coupling; and wherein, in use, the plurality of probes are operable to wirelessly transmit data-carrying signals arising from the sensing electrodes.
Davila-Montero S, Barsakcioglu DY, Jackson A, et al., 2017, Real-time Clustering Algorithm that Adapts to Dynamic Changes in Neural Recordings, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 690-693, ISSN: 0271-4302
De Marcellis A, Palange E, Faccio M, et al., 2017, A 250Mbps 24pJ/bit UWB-inspired Optical Communication System for Bioimplants, Turin, Italy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 132-135
Feng P, Constandinou TG, Yeon P, et al., 2017, Millimeter-Scale Integrated and Wirewound Coils for Powering Implantable Neural Microsystems, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 488-491
Gao C, Ghoreishizadeh S, Liu Y, et al., 2017, On-chip ID Generation for Multi-node Implantable Devices using SA-PUF, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681, ISSN: 0271-4302
Ghoreishizadeh S, Constandinou TG, 2017, On-chip Random ID Generation
Ghoreishizadeh S, Haci D, Liu Y, et al., 2017, Four-Wire Interface ASIC for a Multi-Implant Link, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Pages: 3056-3067, ISSN: 1549-8328
This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical ‘optrodes’ that facilitate a bidirectional neural interface (electrical recording, optical stimulation), and chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate(up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) which is superimposed on a power carrier. On-chip power management provides an unregulated 5V DC supply with up to 2.5mA output current for stimulation, and two regulated voltages (3.3V and 3V) with 60 dB PSRR for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35 um CMOS technology, occupying 1.5mm2 silicon area,and consumes a quiescent current of 91.2u A. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.
Ghoreishizadeh SS, Haci D, Liu Y, et al., 2017, A 4-Wire Interface SoC for Shared Multi- Implant Power Transfer and Full-duplex Communication, 8th IEEE Latin American Symposium on Circuits & Systems (LASCAS), Publisher: IEEE
Guven O, Eftekhar A, Kindt W, et al., 2017, Low-Power Real-Time ECG Baseline Wander Removal: Hardware Implementation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, ISSN: 0271-4302
Haci D, Liu Y, Constandinou TG, 2017, 32-Channel Ultra-Low-Noise Arbitrary Signal Generation Platform for Biopotential Emulation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701, ISSN: 0271-4302
Leene L, Constandinou TG, 2017, A 2.7uW/Mips, 0.88GOPS/mm^2 Distributed Processor for Implantable Brain Machine Interfaces, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 360-363
This paper presents a scalable architecture in 0.18u m CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributedprocessor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7uW/MIPS with a total chip area of 1.37mm2. This configuration executes 1024 instructions on each core at 20MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.
Leene L, Constandinou TG, 2017, A 0.5V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2619-2622, ISSN: 2379-447X
This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nanometre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which isnot well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked ΔΣ behavior which is useful on-chip characterizationand interfacing with synchronous systems. A 0.5V instrumentation system is implemented using a 65nm TSMC technology to realize a highly compact footprint that is 0.006mm2 in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 Vrms input referred noise for the given 810nW total system power budget corresponding to an NEF of 1.64.
Leene L, Constandinou TG, 2017, A 0.016² 12b ΔΣSAR With 14fJ/conv. for ultra low power biosensor arrays, IEEE Transactions on Circuits and Systems. Part 1: Regular Papers, Vol: 64, Pages: 2655-2665, ISSN: 1549-8328
The instrumentation systems for implantable brain-machine interfaces represent one of the most demanding applications for ultra low-power analogue-to-digital-converters (ADC) to date. To address this challenge, this paper proposes a ΔΣSAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0-2 MASH topology. This configuration uses a specialized FIR window to decimate the ΔΣ modulator output and reject mismatch errors from the SAR quantizer, which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision. A fully differential prototype was fabricated using 0.18 μm CMOS to demonstrate 10.8 ENOB precision with a 0.016 mm² silicon footprint. Moreover, a 14 fJ/conv figure-of-merit can be achieved, while resolving signals with the maximum input amplitude of ±1.2,Vpp sampled at 200 kS/s. The ADC topology exhibits a number of promising characteristics for both high speed and ultra low-power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio, which are critical parameters for many sensor applications.
Leene L, Constandinou TG, 2017, Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Pages: 3003-3012, ISSN: 1549-8328
The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth- order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure- of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst addition- ally offering direct integration with digital systems.
Liu Y, Luan S, Williams I, et al., 2017, A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput, IEEE Transactions on Biomedical Circuits and Systems, Vol: 11, Pages: 1344-1355, ISSN: 1932-4545
Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.
Luan S, Williams I, De-Carvalho F, et al., 2017, Standalone headstage for neural recording with real-time spike sorting and data logging, BNA Festival of Neuroscience, Publisher: The British Neuroscience Association Ltd
Luo J, Firfilionis D, Ramezani R, et al., 2017, Live demonstration: a closed-loop cortical brain implant for optogenetic curing epilepsy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 169-169
Maslik M, Liu Y, Lande TSB, et al., 2017, A Charge-Based Ultra-Low Power Continuous-Time ADC for Data Driven Neural Spike Processing, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, ISSN: 0271-4302
Mifsud A, Haci D, Ghoreishizadeh S, et al., 2017, Adaptive Power Regulation and Data Delivery for Multi-Module Implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 584-587
Szostak K, Mazza F, Maslik M, et al., 2017, Microwire-CMOS Integration of mm-Scale Neural Probes for Chronic Local Field Potential Recording, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 492-495
Szostak KM, Grand L, Constandinou TG, 2017, Neural Interfaces for Intracortical Recording: Requirements, Fabrication Methods, and Characteristics, FRONTIERS IN NEUROSCIENCE, Vol: 11, ISSN: 1662-453X
Troiani F, Nikolic K, Constandinou TG, 2017, Optical coherence tomography for compound action potential detection: a computational study, Conference on Optical Coherence Imaging Techniques and Imaging in Scattering Media II, Publisher: SPIE-INT SOC OPTICAL ENGINEERING, ISSN: 0277-786X
Barsakcioglu DY, Constandinou TG, 2016, A 32-Channel MCU-based Feature Extraction and Classification for Scalable On-node Spike Sorting, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1310-1313, ISSN: 0271-4302
De Marcellis A, Palange E, Faccio M, et al., 2016, A New Optical UWB Modulation Technique for 250Mbps Wireless Link in Implantable Biotelemetry Systems, 30th Eurosensors Conference, Publisher: ELSEVIER SCIENCE BV, Pages: 1676-1680, ISSN: 1877-7058
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