Publications
276 results found
Luan S, Williams I, Maslik M, et al., 2018, Compact standalone platform for neural recording with real-time spike sorting and data logging, Journal of Neural Engineering, Vol: 15, Pages: 1-13, ISSN: 1741-2552
Objective. Longitudinal observation of single unit neural activity from largenumbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective Brain Machine Interfaces (BMIs). These recordings generate enormous amounts of data for transmission & storage, and typically require o ine processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: 1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); 2) producing real-time, low-latency, spike sorted data; and 3) long term untethered operation. Approach. We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. Main results. The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 hours at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24-hour initial recording in a nonhuman primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. Signi cance The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals { revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and veri able output suitable f
Troiani F, Nikolic K, Constandinou TG, 2018, Simulating optical coherence tomography for observing nerve activity: a finite difference time domain bi-dimensional model, PLoS ONE, Vol: 13, Pages: 1-14, ISSN: 1932-6203
We present a finite difference time domain (FDTD) model for computation of A line scans in time domain optical coherence tomography (OCT). The OCT output signal is created using two different simulations for the reference and sample arms, with a successive computation of the interference signal with external software. In this paper we present the model applied to two different samples: a glass rod filled with water-sucrose solution at different concentrations and a peripheral nerve. This work aims to understand to what extent time domain OCT can be used for non-invasive, direct optical monitoring of peripheral nerve activity.
Ramezani R, Liu Y, Dehkhoda F, et al., 2018, On-probe neural interface ASIC for combined electrical recording and optogenetic stimulation, IEEE Transactions on Biomedical Circuits and Systems, Vol: 12, Pages: 576-588, ISSN: 1932-4545
Neuromodulation technologies are progressing from pacemaking and sensory operations to full closed-loop control. In particular, optogenetics—the genetic modification of light sensitivity into neural tissue allows for simultaneous optical stimulation and electronic recording. This paper presents a neural interface application-specified integrated circuit (ASIC) for intelligent optoelectronic probes. The architecture is designed to enable simultaneous optical neural stimulation and electronic recording. It provides four low noise (2.08 μVrms) recording channels optimized for recording local field potentials (LFPs) (0.1–300 Hz bandwidth, ± 5 mV range, sampled 10-bit@4 kHz), which are more stable for chronic applications. For stimulation, it provides six independently addressable optical driver circuits, which can provide both intensity (8-bit resolution across a 1.1 mA range) and pulse-width modulation for high-radiance light emitting diodes (LEDs). The system includes a fully digital interface using a serial peripheral interface (SPI) protocol to allow for use with embedded controllers. The SPI interface is embedded within a finite state machine (FSM), which implements a command interpreter that can send out LFP data whilst receiving instructions to control LED emission. The circuit has been implemented in a commercially available 0.35 μm CMOS technology occupying a 1.95 mm × 1.10 mm footprint for mounting onto the head of a silicon probe. Measured results are given for a variety of bench-top, in vitro and in vivo experiments, quantifying system performance and also demonstrating concurrent recording and stimulation within relevant experimental models.
Maslik M, Liu Y, Lande TS, et al., 2018, Continuous-time acquisition of biosignals using a charge-based ADC topology, IEEE Transactions on Biomedical Circuits and Systems, Vol: 12, Pages: 471-482, ISSN: 1932-4545
This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of ≈5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35 μm CMOS technology occupying a compact footprint of 0.12 mm 2 . Silicon verified measurements demonstrate an 8-bit resolution and a 4 kHz bandwidth with static power consumption of 3.75 μW from a 1.5 V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39 pJ energy per conversion.
Leene L, Maslik M, Feng P, et al., 2018, Autonomous SoC for neural local field potential recording in mm-scale wireless implants, IEEE International Symposium on Circuits and Systems, Publisher: IEEE, Pages: 1-5, ISSN: 2379-447X
Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency when observing neural activity over a long period of time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing local field potentials (LFPs) only, chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a ΔΣ based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 μm CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.77μVrms. The resulting electronics has a core area of 2.1 mm2 and a power budget of 92 μW
Liu Y, Pereira J, Constandinou TG, 2018, Event-driven processing for hardware-efficient neural spike sorting, Journal of Neural Engineering, Vol: 15, Pages: 1-14, ISSN: 1741-2552
Objective. The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing. Approach. (1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability. Main results. It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources. Significance. By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.
Williams I, Leene L, Constandinou TG, 2018, Next Generation Neural Interface Electronics, Circuit Design Considerations for Implantable Devices, Editors: Cong, Publisher: River Publishers, Pages: 141-178, ISBN: 978-87-93519-86-2
Cavuto ML, Winter AG, Constandinou T, 2018, Apparatus and Method for Inserting Electrode-based Probes into Biological Tissue
Liu Y, Luan S, Williams I, et al., 2017, A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput, IEEE Transactions on Biomedical Circuits and Systems, Vol: 11, Pages: 1344-1355, ISSN: 1932-4545
Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.
Rapeaux A, Brunton E, Nazarpour K, et al., 2017, Recovery Dynamics of the High Frequency Alternating Current Nerve Block
Objective: High-Frequency alternating current (HFAC) nerve block has great potential for neuromodulation-based therapies. However nerve function recovery dynamics after a block is highly understudied. This study aims to characterise the recovery dynamics of neural function after an HFAC block. Approach: Experiments were carried out in-vivo to determine blocking efficacy as a function of blocking signal amplitude and frequency, and recovery times as well as recovery completeness was measured within a 0.7s time scale from the end of block. The sciatic nerve was stimulated at 100 Hz during recovery to reduce error to within ±10 ms for measurements of recovery dynamics. The electromyogram (EMG) signals were measured from gastrocnemius medialis and tibialis anterior during trials as an indicator for nerve function. Main Results: The HFAC block was most reliable around 20 kHz, with block thresholds approximately 5 or 6 mA depending on the animal and muscle. Recovery times ranged from 20 to 430 milliseconds and final values spanned relative outputs from approximately 1 to 0.2. Higher blocking signal frequencies and amplitudes increased recovery time and decreased recovery completeness. Significance: These results confirm that recovery dynamics from block depend on blocking signal frequency and amplitude, which is of particular importance for neuromodulation therapies and for comparing results across studies using different blocking signal parameters.
Szostak K, Grand L, Constandinou TG, 2017, Neural interfaces for intracortical recording: requirements, fabrication methods, and characteristics, Frontiers in Neuroscience, Vol: 11, ISSN: 1662-4548
Implantable neural interfaces for central nervous system research have been designed with wire, polymer or micromachining technologies over the past 70 years. Research on biocompatible materials, ideal probe shapes and insertion methods has resulted in building more and more capable neural interfaces. Although the trend is promising, the long-term reliability of such devices has not yet met the required criteria for chronic human application. The performance of neural interfaces in chronic settings often degrades due to foreign body response to the implant that is initiated by the surgical procedure, and related to the probe structure, and material properties used in fabricating the neural interface. In this review, we identify the key requirements for neural interfaces for intracortical recording, describe the three different types of probes- microwire, micromachined and polymer-based probes; their materials, fabrication methods, and discuss their characteristics and related challenges.
Leene L, Constandinou TG, 2017, Time domain processing techniques using ring oscillator-based filter structures, IEEE Transactions on Circuits and Systems Part 1: Regular Papers, Vol: 64, Pages: 3003-3012, ISSN: 1549-8328
The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth- order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure- of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst addition- ally offering direct integration with digital systems.
Constandinou TG, Jackson A, 2017, Implantable Neural Interface
A neural interface arrangement comprising: a plurality of probes for subdural implantation into or onto a human brain, each probe including at least one sensing electrode, a coil for receiving power via inductive coupling, signal processing circuitry coupled to the sensing electrode(s), and means for wirelessly transmitting data-carrying signals arising from the sensing electrode(s); an array of coils for implantation above the dura, beneath the skull, the array of coils being for inductively coupling with the coil of each of the plurality of probes, for transmitting power to the probes; and a primary (e.g. subcutaneous) coil connected to the array of coils, the primary coil being for inductively coupling with an external transmitter device, for receiving power from the external transmitter device; wherein, in use, the primary coil is operable to receive power from the external transmitter device by inductive coupling and to cause the array of coils to transmit power to the plurality of probes by inductive coupling; and wherein, in use, the plurality of probes are operable to wirelessly transmit data-carrying signals arising from the sensing electrodes.
Mifsud A, Haci D, Ghoreishizadeh S, et al., 2017, Adaptive Power Regulation and Data Delivery for Multi-Module Implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 584-587
Feng P, Constandinou TG, Yeon P, et al., 2017, Millimeter-Scale Integrated and Wirewound Coils for Powering Implantable Neural Microsystems, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 488-491
Szostak K, Mazza F, Maslik M, et al., 2017, Microwire-CMOS Integration of mm-Scale Neural Probes for Chronic Local Field Potential Recording, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 492-495
De Marcellis A, Palange E, Faccio M, et al., 2017, A 250Mbps 24pJ/bit UWB-inspired Optical Communication System for Bioimplants, Turin, Italy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 132-135
Luo J, Firfilionis D, Ramezani R, et al., 2017, Live demonstration: a closed-loop cortical brain implant for optogenetic curing epilepsy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 169-169
Ahmadi N, Constandinou TG, Bouganis C-S, 2017, Estimation of neuronal firing rate using Bayesian Adaptive Kernel Smoother (BAKS)
<jats:title>Abstract</jats:title><jats:p>Neurons use sequences of action potentials (spikes) to convey information across neuronal networks. In neurophysiology experiments, information about external stimuli or behavioral tasks has been frequently characterized in term of neuronal firing rate. The firing rate is conventionally estimated by averaging spiking responses across multiple similar experiments (or trials). However, there exist a number of applications in neuroscience research that require firing rate to be estimated on a single trial basis. Estimating firing rate from a single trial is a challenging problem and current state-of-the-art methods do not perform well. To address this issue, we develop a new method for estimating firing rate based on kernel smoothing technique that considers the bandwidth as a random variable with prior distribution that is adaptively updated under a Bayesian framework. By carefully selecting the prior distribution together with Gaussian kernel function, an analytical expression can be achieved for the kernel bandwidth. We refer to the proposed method as Bayesian Adaptive Kernel Smoother (BAKS). We evaluate the performance of BAKS using synthetic spike train data generated by biologically plausible models: inhomogeneous Gamma (IG) and inhomogeneous inverse Gaussian (IIG). We also apply BAKS to real spike train data from non-human primate (NHP) motor and visual cortex. We benchmark the proposed method against the established and previously reported methods. These include: optimized kernel smoother (OKS), variable kernel smoother (VKS), local polynomial fit (Locfit), and Bayesian adaptive regression splines (BARS). Results using both synthetic and real data demonstrate that the proposed method achieves better performance compared to competing methods. This suggests that the proposed method could be useful for understanding the encoding mechanism of neurons in cognitive-related tasks. The proposed method could als
Leene L, Constandinou TG, 2017, A 0.5V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2619-2622, ISSN: 2379-447X
This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nanometre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which isnot well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked ΔΣ behavior which is useful on-chip characterizationand interfacing with synchronous systems. A 0.5V instrumentation system is implemented using a 65nm TSMC technology to realize a highly compact footprint that is 0.006mm2 in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 Vrms input referred noise for the given 810nW total system power budget corresponding to an NEF of 1.64.
Maslik M, Liu Y, Lande TS, et al., 2017, A charge-based ultra-low power continuous-time ADC for data driven neural spike processing, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1420-1423
The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75uW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4uW. The circuit has been implemented in a commercially available 0.35um CMOS technology with core occupying a footprint of 0.12 sq.mm
Haci D, Liu Y, Constandinou TG, 2017, 32-channel ultra-low-noise arbitrary signal generation platform for biopotential emulation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701
This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10kHz bandwidth, 110dB dynamic range and uV-level output noise.
Gao C, Ghoreishizadeh S, Liu Y, et al., 2017, On-chip ID generation for multi-node implantable devices using SA-PUF, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681
This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 m CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.
Guven O, Eftekhar A, Kindt W, et al., 2017, Low-power real-time ECG baseline wander removal: hardware implementation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1571-1574
This paper presents a hardware realisation of a novel ECG baseline drift removal that preserves the ECG signal integrity. The microcontroller implementation detects the fiducial markers of the ECG signal and the baseline wander estimation is achieved through a weighted piecewise linear interpolation. This estimated drift is then removed to recover a “clean” ECG signal without significantly distorting the ST segment. Experimental results using real data from the MIT-BIH Arrhythmia Database (recording 100 and 101) with added baseline wander (BWM1) from the MIT-BIH Noise Stress Database show an average root mean square error of 34.3uV (mean), 30.4u V (median) and 18.4uV (standard deviation) per heart beat.
Dávila-Montero S, Barsakcioglu DY, Jackson A, et al., 2017, Real-time clustering algorithm that adapts to dynamic changes in neural recordings, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 690-693
This work presents a computationally efficient real-time adaptive clustering algorithm that recognizes and adapts to dynamic changes observed in neural recordings. The algorithm consists of an off-line training phase that determines initial cluster positions, and an on-line operation phase that continuously tracks drifts in clusters and periodically verifies acute changes in cluster composition. Analysis of chronic recordings from non-human primates shows that adaptive clustering achieves an improvement of 14% in classification accuracy and demonstrates an ability to recognize acute changes with 78% accuracy, with up to 29% computational efficiency compared to the state-of-the-art. The presented algorithm is suitable for long-term chronic monitoring of neural activity in various applications such as neuroscience research and control of neural prosthetics and assistive devices.
Luan S, Williams I, Maslik M, et al., 2017, Compact Standalone Platform for Neural Recording with Real-Time Spike Sorting and Data Logging
<jats:p>Objective. Longitudinal observation of single unit neural activity from large numbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective Brain Machine Interfaces (BMIs). These recordings generate enormous amounts of data for transmission & storage, and typically require offline processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: 1) reducing the data bandwidth by circa 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission); 2) producing real-time, low-latency, spike sorted data; and 3) long term untethered operation. Approach. We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw data as well as the spike sorted data. Main results. The system can successfully record 32 channels of raw and/or spike sorted data for well over 24 hours at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24-hour initial recording in a non-human primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. Significance The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals revealing insights that are not attainable through scheduled recording sessions and provides a robust, low-latency, low-bandwidth output suitable for BMIs, closed loop neuromodulation, wireless transmission and long term data logging.</jats:p>
Ghoreishizadeh S, Haci D, Liu Y, et al., 2017, Four-Wire Interface ASIC for a Multi-Implant Link, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Pages: 3056-3067, ISSN: 1549-8328
This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical ‘optrodes’ that facilitate a bidirectional neural interface (electrical recording, optical stimulation), and chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate(up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) which is superimposed on a power carrier. On-chip power management provides an unregulated 5V DC supply with up to 2.5mA output current for stimulation, and two regulated voltages (3.3V and 3V) with 60 dB PSRR for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35 um CMOS technology, occupying 1.5mm2 silicon area,and consumes a quiescent current of 91.2u A. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.
Troiani F, Nikolic K, Constandinou TG, 2017, Optical coherence tomography for compound action potential detection: a computational study, SPIE/OSA European Conferences on Biomedical Optics (ECBO), Publisher: Optical Society of America / SPIE, Pages: 1-3
The feasibility of using time domain optical coherence tomography (TD-OCT) to detect compound action potential in a peripheral nerve and the setup characteristics, are studied through the use of finite-difference time-domain (FDTD) technique.
Luo JW, Firfilionis D, Ramezani R, et al., 2017, Live demonstration: A closed-loop cortical brain implant for optogenetic curing epilepsy
A closed-loop optogenetic system for curing epilepsy is presented in this work. As it shown at figure 1, the system consists of a cortical brain implant with LEDs and recording electrodes, a customer designed CMOS chip[1][2][3] and a controller. The brain activities are recorded by the implant with recording electronics in a CMOS chip, the signals are processed by the controller, and the results are send back to the CMOS chip for delivering LED stimulation commands.
This data is extracted from the Web of Science and reproduced under a licence from Thomson Reuters. You may not copy or re-distribute this data in whole or in part without the written consent of the Science business of Thomson Reuters.