Imperial College London

ProfessorWayneLuk

Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
to

619 results found

Thomas DB, Luk W, 2008, Estimation of Sample Mean and Variance for Monte-Carlo Simulations, International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 89-96

Conference paper

Thomas DB, Luk W, 2008, FPGA-Optimised High-Quality Uniform Random Number Generators, 16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Publisher: ASSOC COMPUTING MACHINERY, Pages: 235-244

Conference paper

Thomas DB, Luk W, 2008, Resource Efficient Generators for the Floating-point Uniform and Exponential Distributions, 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Publisher: IEEE, Pages: 102-107, ISSN: 2160-0511

Conference paper

Jin Q, Thomas DB, Luk W, Cope Bet al., 2008, Exploring reconfigurable architectures for binomial-tree pricing models, 4th International Workshop on Applied Reconfigurable Computing, Publisher: SPRINGER-VERLAG BERLIN, Pages: 245-+, ISSN: 0302-9743

Conference paper

Atasu K, Todman T, Mencer O, Luk Wet al., 2008, Optimal Implementation of Combinational Logic on Look-up Tables, The Fourth Conference on Ph.D. Research in Microelectronics and Electronics (PRIME'08)

Conference paper

Mak T, Sedcole P, Cheung PYK, Luk Wet al., 2008, Wave-Pipelined Signaling for On-FPGA Communication, International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 9-+

Conference paper

Mak T, D'Alessandro C, Sedcole P, Cheung PYK, Yakovlev A, Luk Wet al., 2008, Global Interconnections in FPGAs: Modeling and Performance Analysis, ACM International Workshop on System Level Interconnect Prediction, Publisher: ASSOC COMPUTING MACHINERY, Pages: 51-58

Conference paper

Atasu K, Mencer O, Luk W, Ozturan C, Dundar Get al., 2008, Fast Custom Instruction Identification by Convex Subgraph Enumeration, 19th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

Conference paper

Cope B, Cheung PYK, Luke W, 2008, Systematic Design Space Exploration for Customisable Multi-Processor Architectures, International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation, Publisher: IEEE, Pages: 57-+

Conference paper

Becker T, Jamieson P, Luk W, Cheung PYK, Rissa Tet al., 2008, TOWARDS BENCHMARKING ENERGY EFFICIENCY OF RECONFIGURABLE ARCHITECTURES, 18th International Conference on Field Programmable and Logic Applications, Publisher: IEEE, Pages: 690-+, ISSN: 1946-1488

Conference paper

Cope B, Cheung PYK, Luk W, 2008, Using reconfigurable logic to optimise GPU memory accesses, Design, Automation and Test in Europe Conference and Exhibition (DATE 08), Publisher: IEEE, Pages: 42-+, ISSN: 1530-1591

Conference paper

Lam YM, Coutinho JGF, Luk W, Leong PHWet al., 2008, MAPPING AND SCHEDULING WITH TASK CLUSTERING FOR HETEROGENEOUS COMPUTING SYSTEMS, 18th International Conference on Field Programmable and Logic Applications, Publisher: IEEE, Pages: 275-+, ISSN: 1946-1488

Conference paper

Ho CH, Leong PHW, Luk W, Wilton SJEet al., 2008, RAPID ESTIMATION OF POWER CONSUMPTION FOR HYBRID FPGAS, 18th International Conference on Field Programmable and Logic Applications, Publisher: IEEE, Pages: 227-+, ISSN: 1946-1488

Conference paper

Lam A, Wilton SJE, Leong P, Luk Wet al., 2008, AN ANALYTICAL MODEL DESCRIBING THE RELATIONSHIPS BETWEEN LOGIC ARCHITECTURE AND FPGA DENSITY, 18th International Conference on Field Programmable and Logic Applications, Publisher: IEEE, Pages: 221-+, ISSN: 1946-1488

Conference paper

Lam YM, Coutinho JGF, Luk W, Leong PHWet al., 2008, Unrolling-based loop mapping and scheduling, International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 321-+

Conference paper

Yu CW, Smith AM, Luk W, Leong PHW, Wilton SJEet al., 2008, OPTIMIZING COARSE-GRAINED UNITS IN FLOATING POINT HYBRID FPGA, International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 57-+

Conference paper

Yiu KFC, Ho CH, Grbric N, Lu Y, Shi X, Luk Wet al., 2008, Reconfigurable Acceleration of Microphone Array Algorithms for Speech Enhancement, 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Publisher: IEEE, Pages: 203-+, ISSN: 2160-0511

Conference paper

Lamoureux J, Luk W, 2008, An overview of low-power techniques for field-programmable gate arrays, 3rd NASA/ESA Conference on Adaptive Hardware and Systems, Publisher: IEEE COMPUTER SOC, Pages: 338-345

Conference paper

Yiu K-FC, Lu Y, Shi X, Luk Wet al., 2008, FPGA acceleration of a subband beamforming algorithm for speech enhancement, CISP 2008: FIRST INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING, VOL 5, PROCEEDINGS, Pages: 742-746

Journal article

Yu CW, Lamoureux J, Wilton SJE, Leong PHW, Luk Wet al., 2008, The coarse-grained/fine-grained logic interface in FPGAs with embedded floating-point arithmetic units, 2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS, Pages: 63-+

Journal article

Lam YM, Coutinho JGF, Luk W, Leong RHWet al., 2008, Integrated hardware/software codesign for heterogeneous computing systems, 2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS, Pages: 217-+

Journal article

Echeverria P, Thomas DB, Lopez-Vallejo M, Luk Wet al., 2008, An FPGA run-time parameterisable Log-normal random number generator, 4th International Workshop on Applied Reconfigurable Computing, Publisher: SPRINGER-VERLAG BERLIN, Pages: 221-+, ISSN: 0302-9743

Conference paper

Koester M, Luk W, Brown G, 2008, A HARDWARE COMPILATION FLOW FOR INSTANCE-SPECIFIC VLIW CORES, 18th International Conference on Field Programmable and Logic Applications, Publisher: IEEE, Pages: 618-+, ISSN: 1946-1488

Conference paper

Yusuf S, Luk W, Sloman M, Dulay N, Lupu EC, Brown Get al., 2008, Reconfigurable architecture for network flow analysis, International Conference on Engineering of Reconfigurable Systems and Algorithms, Pages: 57-65

This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high network data rates. Our approach maps the performance-critical tasks of packet classification and flow monitoring into reconfigurable hardware, such that multiple flows can be processed in parallel. We explore the scalability of our system, showing that it can support flows at multi-gigabit rate; this is faster than most software-based solutions where acceptable data rates are typically no more than 100 million bits per second.

Conference paper

Yusuf S, Luk W, Sloman M, Dulay N, Lupu ECet al., 2008, Reconfigurable architecture for network flow analysis, IEEE Transactions on VLSI System, Vol: 16, Pages: 57-65, ISSN: 1063-8210

Journal article

Fu H, Mencer O, Luk W, 2008, Optimizing Residue Arithmetic on FPGAs, International Conference on Field-Programmable Technology 2008, Publisher: IEEE, Pages: 41-48

Conference paper

Yu CW, Lamoureux J, Wilton SJE, Leong PHW, Luk Wet al., 2008, The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units, International Journal of Reconfigurable Computing, Vol: 2008, Pages: 1-10, ISSN: 1687-7195

<jats:p>This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) embedded memory should be located between the FPUs; and (5) connecting higher I/O density coarse-grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used.</jats:p>

Journal article

Fidjeland A, Luk W, Muggleton S, 2008, A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming., Publisher: British Computer Society, Pages: 318-330

Conference paper

Mak TST, Sedcole NP, Cheung PYK, Luk Wet al., 2008, High-throughput interconnect wave-pipelining for global communication in FPGAs., Publisher: ACM, Pages: 258-258

Conference paper

Atasu K, Ozturan C, Dundar G, Mencer O, Luk Wet al., 2008, CHIPS: Custom Hardware Instruction Processor Synthesis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol: 27, Pages: 528-541

This paper describes an integer linear programming (ILP) based system called CHIPS that identifies custom instructions for critical code segments, given the available data bandwidth and transfer latencies between custom logic and a baseline processor with architecturally visible state registers. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions. We describe a design flow to identify promising area, performance and code size tradeoffs. We study the effect of input/output constraints, register file ports, and compiler transformations such as if-conversion. Our experiments show that, in most cases, the solutions with the highest performance are identified when the input/output constraints are removed. However, input/output constraints help our algorithms identify frequently used code segments, reducing the overall area overhead. Results for 11 benchmarks covering cryptography and multimedia are shown, with speed-ups between 1.7 and 6.6 times, code size reductions between 6\% and 72\%, and area costs ranging between 12 and 256 adders for maximum speed-up. Our ILP based approach scales well: benchmarks with basic blocks consisting of more than 1000 instructions can be optimally solved, most of the time within a few seconds.

Journal article

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