Imperial College London

ProfessorWayneLuk

Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
to

619 results found

Ho CH, Yu CW, Leong PHW, Luk W, Wilton SJEet al., 2007, Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications, Amsterdam, International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 196-201

Conference paper

Fidjeland A, Luk W, 2006, Archlog: High-level synthesis of reconfigurable multiprocessors for logic programming, Pages: 335-340

This paper presents Archlog, a language and framework for designing multiprocessor architectures in the logic programming domain. Our goal is to enable application developers in areas such as machine learning and cognitive robotics to produce high-performance designs for reconfigurable devices, without detailed knowledge of hardware development. The Archlog framework provides a high level of abstraction, enabling rapid system generation while supporting high performance. In this paper we present the Archlog language and its library-based compilation framework, which makes use of a customisable logic programming processor. The system generates multiple designs, with different trade-offs in the use of reconfigurable logic and embedded memories. An implementation of a multiprocessor for the machine learning system Progol on a 40MHz XC2V6000 FPGA is 10 times faster than a 2GHz Pentium 4 processor. © 2006 IEEE.

Conference paper

Derbyshire A, Becker T, Luk W, 2006, Incremental elaboration for run-time reconfigurable hardware designs, Pages: 93-102

We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in application specific integrated circuits (ASICs) or microprocessors. These systems can often provide substantially more computational power than microprocessors and support higher exibility than ASICs. The compilation of hardware during run time, however, can add significant run-time overhead to these systems. We introduce a novel compilation technique called incremental elaboration, which enables circuits to be dynamically generated during run time. We propose a set-based model for incremental elaboration, and explain how it can be used in the hardware compilation process. Our approach is illustrated by various designs, particulary those for pattern matching and shape-adaptive template matching. Copyright 2006 ACM.

Conference paper

Pell O, Luk W, 2006, Compiling higher-order polymorphic hardware descriptions into parametrised vhdl libraries with flexible placement information, Pages: 125-130

We present a framework for generating parametrised high-performance IP library cores from high level descriptions. Our system is based around the Quartz language which provides advanced features such as polymorphism, overloading, higher-order combinators and formal reasoning while supporting precise and flexible control of layout for efficient FPGA design and compiling into parametrised VHDL libraries. We illustrate the application of our system to the design of several example circuits; placement constraints generated by our system can increase clock frequency by up to 25% and can also reduce area. Quartz placement information is flexible, allowing us to easily describe placed circuits which can be compacted when specialised for particular input values. We describe a self-specialising multiplier which adjusts component locations when some input bits are known; this multiplier can be easily integrated into larger circuits such as FIR filters or matrix multipliers. © 2006 IEEE.

Conference paper

Bayliss S, Bouganis C, Constantinides GA, Luk Wet al., 2006, An FPGA Implementation of the Simplex Algorithm, Pages: 49-55

Conference paper

Ang S-S, Constantinides GA, Luk W, Cheung PYKet al., 2006, The Cost of Data Dependence in Motion Vector Estimation for Reconfigurable Platforms, Pages: 333-336

Conference paper

Lee D, Abdul Gaffar A, Cheung C, Constantinides G, Luk W, Mencer Oet al., 2006, Accuracy Guaranteed Bit-Width Optimization, IEEE Transactions on Computer-Aided Design, Vol: 25, Pages: 1990-2000, ISSN: 0278-0070

Journal article

Mak S T, Sedcole N P, Cheung, P Y K, Luk Wet al., 2006, On-FPGA Communication Architectures and Design Factors, IEEE International Conference on Field-Programmable Logic, Pages: 161-168

Conference paper

Mak S T, Sedcole N P, Cheung, P Y K, Luk Wet al., 2006, On-FPGA Communication Architectures and Design Factors, IEEE International Conference on Field-Programmable Logic, Pages: 161-168

Conference paper

Lee DU, Villasenor JD, Luk W, Leong PHWet al., 2006, A hardware Gaussian noise generator using the Box-Muller method and its error analysis, IEEE TRANSACTIONS ON COMPUTERS, Vol: 55, Pages: 659-671, ISSN: 0018-9340

Journal article

McKeever S, Luk W, 2006, Provably-correct hardware compilation tools based on pass separation techniques, FORMAL ASPECTS OF COMPUTING, Vol: 18, Pages: 120-142, ISSN: 0934-5043

Journal article

Dimond R, Mencer O, Luk W, 2006, Application-specific customisation of multi-threaded soft processors, 15th International Conference on Field Programmable Logic and Applications, Publisher: INST ENGINEERING TECHNOLOGY-IET, Pages: 173-180, ISSN: 1350-2387

Conference paper

Yusuf S, Luk W, Szeto MKN, Osborne Wet al., 2006, UNITE: Uniform hardware-based network intrusion deTection engine, 2nd International Workshop on Reconfigurable Computing, Publisher: SPRINGER-VERLAG BERLIN, Pages: 389-400, ISSN: 0302-9743

Conference paper

, 2006,

Conference paper

Todman TJ, Constantinides GA, Wilton SJE, Mencer O, Luk W, Cheung PYKet al., 2006, Reconfigurable computing: Architectures and design methods, System-on-Chip: Next Generation Electronics, Pages: 451-494, ISBN: 9780863415524

© 2006 The Institution of Electrical Engineers and 2008 The Institution of Engineering and Technology. This chapter surveys two aspects of reconfigurable computing: architectures and design methods. The main trends in architectures are coarse-grained fabrics, heterogeneous functions and soft cores. The main trends in design methods are special purpose design methods, low power techniques and high-level transformations. We wonder what a survey of reconfigurable computing, written in 2015, will cover?.

Book chapter

Fidjeland A, Luk W, 2006, Archlog: High-level synthesis of reconfigurable multiprocessors for logic programming, 16th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 335-340, ISSN: 1946-1488

Conference paper

Pell O, Luk W, 2006, <bold>COMPILING HIGHER-ORDER POLYMORPHIC HARDWARE DESCRIPTIONS INTO PARAMETRISED VHDL LIBRARIES WITH FLEXIBLE PLACEMENT INFORMATION</bold>, 16th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 125-130, ISSN: 1946-1488

Conference paper

Dimond RG, Mencer O, Luk W, 2006, Combining instruction coding and scheduling to optimize energy in system-on-FPGA, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 175-+

Conference paper

Dimond R, Mencer O, Luk W, 2006, Automating processor customisation: Optimised memory access and resource sharing, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Publisher: IEEE, Pages: 204-+, ISSN: 1530-1591

Conference paper

Fu H, Mencer O, Luk W, 2006, Comparing floating-point and logarithmic number representations for reconfigurable acceleration, 5th IEEE International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 337-+

Conference paper

Rissa T, Cheung PYK, Luk W, 2006, System level design exploration of JPEG 2000 with SoftSONIC virtual hardware platform, 49th IEEE International Midwest Symposium on Circuits and Systems, Publisher: IEEE, Pages: 276-+, ISSN: 1548-3746

Conference paper

Fahmy SA, Bouganis C-S, Cheung PYK, Luk Wet al., 2006, Efficient realtime FPGA implementation of the Trace Transform, 16th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 555-560, ISSN: 1946-1488

Conference paper

, 2006,

Conference paper

, 2006,

Conference paper

Pell O, Luk W, 2006, Generating parametrised hardware libraries from higher-order descriptions, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 297-+

Conference paper

Ho CH, Leong PHW, Luk W, Wilton SJE, Lopez-Buedo Set al., 2006, Virtual embedded blocks: A methodology for evaluating embedded elements in FPGAs, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 35-+

Conference paper

Thomas DB, Bower JA, Luk W, 2006, Hardware architectures for Monte-Carlo based financial simulations, 5th IEEE International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 377-+

Conference paper

Thomas DB, Luk W, 2006, Efficient hardware generation of random variates with arbitrary distributions, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 57-+

Conference paper

Bower JA, Thomas DB, Luk W, Mencer Oet al., 2006, <bold>A Reconfigurable Simulation Framework for Financial Computation</bold>, 3rd IEEE International Conference on Reconfigurable Computing and FPGAs, Publisher: IEEE, Pages: 30-+

Conference paper

Lee D-U, Cheung RCC, Villasenor JD, Luk Wet al., 2006, Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation, 5th IEEE International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 33-39

Conference paper

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