619 results found
McKeever S, Luk W, 2001, Towards provably-correct hardware compilation tools based on pass separation techniques, Pages: 212-227, ISSN: 0302-9743
This paper presents a framework for verifying compilation tools based on parametrised hardware libraries expressed in Pebble, a simple declarative language. Anapproach based on pass separation techniques is described for specifying and verifying Pebble abstraction mechanisms, such as the loop statement.We show how this approach can be used to verify the correctness of the flattening procedure in the Pebble compiler, which also results in a more efficient implementation than a non-verified version. The approach is useful for guiding compiler implementations for Pebble and related languages such as VHDL; it may also form the basis for automating the generation of provably-correct tools for hardware development. © 2001 Springer-Verlag Berlin Heidelberg.
Boullis N, Mencer O, Luk W, et al., 2001, Pipelined Function Evaluation on FPGAs, Pages: 304-306
© 2001 Non IEEE. This paper presents an approach to parameterizing pipelined designs for differentiable function evaluation using lookup tables, adders and multipliers. Trade-offs involved in implementing the lookup table as a full table or as bipartite tables are discussed. In case of implementations with a lookup table and a multiplier, equations estimating approximation errors and rounding errors can be used to parameterize the hardware unit. The method is implemented as part of the PAM-Blox module generation environment. An example shows that our approach produces competitive designs with data widths up to 20 bits when compared with shift-and-add based CORDIC units; it can be used for larger data widths when evaluating functions not supported by CORDIC.
McKeever S, Luk W, 2001, A declarative framework for developing parametrised hardware libraries, New York, 8th IEEE international conference on electronics, circuits and systems, St Julians, Malta, 2001, Publisher: IEEE, Pages: 1635-1638
Constantinides GA, Cheung PYK, Luk W, 2001, The multiple wordlength paradigm, Proceedings of the 9th annual IEEE symposium on field-programmable custom computing machines (FCCM'01), Pages: 51-60
Constantinides GA, Cheung PYK, Luk W, 2001, Heuristic Datapath Allocation for Multiple Wordlength Systems, Pages: 791-796
Luk W, Yasuf S, Nagarajan R, 2001, Incremental development of hardware packet filters, Athens, International conference on engineering of reconfigurable systems and algorithms (ERSA 2001), Las Vegas, Nevada, 2001, Publisher: C S R e A Press, Pages: 115-118
Jardine FM, Burland JB, Standing JR, 2001, Introduction, Building response to tunnelling: case studies from the Jubilee Line Extension, London: volume 1: projects and methods, Editors: Burland, Standing, Jardine, London, Publisher: CIRIA and Thomas Telford, Pages: 1-8, ISBN: 9780727730176
Visavakul C, Cheung PYK, Luk W, 2001, A digit-serial structure for reconfigurable multipliers, Berlin, 11th conference on field programmable logic and applications, Belfast, August 2001, Publisher: Springer, Pages: 565-573
Arnold J, Luk W, Pocek K, 2000, Guest editors' introduction, JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, Vol: 24, Pages: 127-127, ISSN: 0922-5773
Derbyshire A, Luk W, 2000, Combining serialisation and reconfiguration for convolver designs, IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 344-346
Weinhardt M, Luk W, 2000, Evaluating hardware compilation techniques, IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 333-334
Derbyshire A, Luk W, 2000, Combining serialisation and reconfiguration for FPGA designs, Pages: 636-645, ISSN: 0302-9743
© Springer-Verlag Berlin Heidelberg 2000. This paper describes a tool framework and techniques for combining serialisation and reconfiguration to produce efficient designs. Convolver and matrix multiplier designs are examined. Several optimisation techniques, such as restructuring and pipeline morphing, are presented with an analysis of their impact on performance and resource usage. The proposed techniques do not require the basic processing element to be modified. An estimate of the performance of the serial designs is given when mapped using distributed arithmetic and constant multiplier cores onto a Xilinx Virtex FPGA.
Zhang XJ, Ng KW, Luk W, 2000, A combined approach to high-level synthesis for dynamically reconfigurable systems, Pages: 361-370, ISSN: 0302-9743
© Springer-Verlag Berlin Heidelberg 2000. In this paper, two complementary design models and related synthesis techniques are combined to capture behavioral and structural information in modelling and synthesizing a dynamically reconfigurable system. The proposed formulation is achieved by using finite domain constraints and related constraint-solving techniques offered by constraint logic programming. Our formulation represents operation-level temporal constraints and dynamic resource constraints in a unified model. Different synthesis tasks, such as temporal partitioning, scheduling and dynamic module allocation can be modelled in this framework, enabling the discovery of an optimal or near optimal solutions. Experiments have been carried out using a prototype of the high-level synthesis system implemented in CHIP, a constraint logic programming system. Current experimental results show that our approach can provide promising synthesis results in terms of the synthesis time and the number of reconfigurations.
Styles H, Luk W, 2000, Customising graphics applications: Techniques and programming interface, IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 77-87
Constantinides GA, Cheung PYK, Luk W, 2000, Roundoff-noise shaping in filter design, IEEE International Symposium on Circuits and Systems (ISCAS 2000), Publisher: IEEE, Pages: 57-60
Seng PS, Luk W, Cheung PYK, 2000, Flexible Instruction Processors, Proc. Int. Conference on Compilers, architecture, and synthesis for embedded systems, Publisher: ACM Press, Pages: 193-200
Constantinides GA, Cheung PYK, Luk W, 2000, Multiple Precision for Resource Minimization, Pages: 307-308
Shirazi N, Luk W, Cheung PYK, 2000, Framework and Tools for Run-Time Reconfiggurable Designs, IEE Proc.Computers and Digital Techniques, Vol: 147, Pages: 147-152
Gause J, Cheung PYK, Luk W, 2000, Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT, Field-Programmable Logic and Applications, LCNS 1896, Pages: 96-105
Haynes SD, Cheung PYK, Luk W, et al., 2000, Video Image Processing with the SONIC Architecture, IEEE Computer, Vol: 33, Pages: 50-57
Constantinides GA, Cheung PYK, Luk W, 2000, Optimal Datapath Allocation for Multiple-Wordlength Systems, IEE Electronics Letters, Vol: 36, Pages: 1508-1509
Constantinides GA, Cheung PYK, Luk W, 2000, Multiple-Wordlength Resource Binding, Field Programmable Logic
Constantinides GA, Cheung PYK, Luk W, 1999, Truncation noise in fixed-point SFGs, Electronics Letters, Vol: 35, Pages: 2013-2014, ISSN: 0013-5194
A new model for predicting truncation error variance in fixed-point filter implementations is introduced. The proposed model is shown to be more accurate than existing models, particularly for some direct hardware implementations. In addition, some comments are made on the applicability of existing error models.
Luk W, Cheung PYK, Lee TK, et al., 1999, Reconfigurable computing for augmented reality, Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, Publisher: IEEE Computer Society Press, Pages: 136-145
Constantinides GA, Cheung PYK, Luk W, 1999, Synthia: Synthesis of Interacting Automata targeting LUT-based FPGAs, Field-Programmable Logic Application, Proceedings of FPL'99, Sept 1999, Publisher: Springer Verlag
Constantinides GA, Cheung PYK, Luk W, 1999, Truncation noise in fixed-point signal-flow graphs, Electronics Lett., Vol: 35, Pages: 2012-2014
Constantinides GA, Cheung PYK, Luk W, 1999, Truncation noise in fixed-point SFGs, Electronics Letters, Vol: 35, Pages: 2012-2014
Haynes SD, Cheung PYK, Luk W, et al., 1999, SONIC - a plug-in architecture for video processing, Proc IEEE Symp. on Field-Programmable Custom Computing Machines, Publisher: IEEE Computer Society Press, Pages: 280-281
Benyamin D, Luk W, Villasenor J, 1999, Optimizing FPGA-based vector product designs, Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, Publisher: IEEE Computer Society Press, Pages: 188-197
Shirazi N, Luk W, Cheung PYK, 1999, Quantitative analysis of run-time reconfigurable database search, Field-Programmable Logic and Applications, Springer LNCS 1673, Pages: 253-263
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