Imperial College London

ProfessorWayneLuk

Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
to

619 results found

Guo S, Luk W, 1995, Compiling Ruby into FPGAs, Field Programmable Logic and Applications, Publisher: Springer, Pages: 188-197

Conference paper

Lawrence A, Kay A, Luk W, Nomura T, Page Iet al., 1995, Using reconfigurable hardware to speed up product development and performance, Field Programmable Logic and Applications, Publisher: Springer, Pages: 111-118

Conference paper

Luk W, 1995, A declarative approach to incremental custom computing, Proceedings of IEEE Symp. on FPGAs for Custom Computing Machines, Publisher: IEEE Computer Society Press, Pages: 164-172

Conference paper

, 1995, Field-Programmable Logic and Applications, 5th International Workshop, FPL '95, Oxford, UK, August 29 - September 1, 1995, Proceedings, Publisher: Springer

Conference paper

GUO S, LUK W, PROBERT P, 1994, DEVELOPING PARALLEL ARCHITECTURES FOR RANGE AND IMAGE SENSORS, 1994 IEEE International Conference on Robotics and Automation, Publisher: I E E E, COMPUTER SOC PRESS, Pages: 2205-2210, ISSN: 1050-4729

Conference paper

LUK W, LAWRENCE A, LOK V, PAGE I, STAMPER Ret al., 1994, PARAMETRISED NEURAL NETWORK DESIGN AND COMPILATION INTO HARDWARE, International Workshop on Artificial Intelligence and Neural Networks, Publisher: PLENUM PRESS DIV PLENUM PUBLISHING CORP, Pages: 197-206

Conference paper

Newman M, Luk W, Page I, 1994, Constraint-based hierarchical placement of parallel programs, Pages: 220-229, ISSN: 0302-9743

© Springer-Verlag Berlin Heidelberg 1994. This paper continues our investigation into the feasibility of exploiting the structure of a parallel program to guide its hardware implementation. We review previous work, and present our new approach to the problem based upon placing netlists hierarchically. It is found that appropriate constraints can be derived from the source code in a straight-forward way, and this information can be used to guide the subsequent placement routines. Comparisons with traditional placement procedures based on simulated annealing are given.

Conference paper

Luk W, Wu T, 1994, Towards a declarative framework for hardware-software codesign., Publisher: IEEE Computer Society, Pages: 181-188

Conference paper

Brown G, Luk W, O'Leary J, 1994, Retargeting a hardware compiler proof using protocol converters., Publisher: IEEE, Pages: 54-63

Conference paper

LUK W, 1993, PIPELINING AND TRANSPOSING HETEROGENEOUS ARRAY DESIGNS, JOURNAL OF VLSI SIGNAL PROCESSING, Vol: 5, Pages: 7-20, ISSN: 0922-5773

Journal article

Luk WWC, 1993, Systematic serialisation of array-based architectures, Integration, the VLSI Journal, Vol: 14, Pages: 333-360, ISSN: 0167-9260

This paper describes the use of Ruby, a language of functions and relations, to develop serialised implementations of array-based architectures. Our Ruby expressions contain parameters which can be varied to produce a wide range of designs with different space-time trade-offs. Such expressions can be obtained by applying correctness-preserving transformations to an initial simple description. This approach provides a unified treatment of serialisation schemes similar to LPGS (Locally Parallel Globally Sequential) and LSGP (Locally Sequential Globally Parallel) partitioning methods, and will be illustrated by the development of a variety of circuits for convolution. © 1993.

Journal article

Luk WWC, 1992, Transformation techniques for serial array design, Proceedings of the International Conference on Application, Pages: 574-588

This paper describes a design framework for developing application-specific serial array circuits. Starting from a description of the state-transition logic or a fully-parallel architecture, correctness-preserving transformations are employed to derive a wide range of implementations with different space-time trade-offs. The approach has been used in synthesizing designs based on Field-Programmable Gate Arrays, and will be illustrated by the development of a number of circuits including sorters and convolvers.

Journal article

LUK W, BROWN G, 1990, A SYSTOLIC LRU PROCESSOR AND ITS TOP-DOWN DEVELOPMENT, SCIENCE OF COMPUTER PROGRAMMING, Vol: 15, Pages: 217-233, ISSN: 0167-6423

Journal article

LUK W, 1990, SYSTOLIC BAND-MATRIX MULTIPLIERS, ELECTRONICS LETTERS, Vol: 26, Pages: 403-405, ISSN: 0013-5194

Journal article

LUK W, 1990, ANALYZING PARAMETRISED DESIGNS BY NONSTANDARD INTERPRETATION, INTERNATIONAL CONF ON APPLICATION SPECIFIC ARRAY PROCESSORS ( ASAP-90 ), Publisher: I E E E, COMPUTER SOC PRESS, Pages: 133-144

Conference paper

LUK W, 1989, REGULAR PIPELINED MULTIPLIERS, ELECTRONICS LETTERS, Vol: 25, Pages: 1405-1407, ISSN: 0013-5194

Journal article

LUK W, JONES G, SHEERAN M, 1989, COMPUTER-BASED TOOLS FOR REGULAR ARRAY DESIGN, 3RD INTERNATIONAL CONF ON SYSTOLIC ARRAYS : SYSTOLIC ARRAY PROCESSORS, Publisher: PRENTICE HALL, Pages: 589-598

Conference paper

LUK W, JONES G, 1988, SYSTOLIC RECURSIVE FILTERS, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Vol: 35, Pages: 1067-1068, ISSN: 0098-4094

Journal article

LUK W, JONES G, 1987, SYSTOLIC ARRAYS FOR RECURSIVE DIGITAL FILTERING, ELECTRONICS LETTERS, Vol: 23, Pages: 1174-1175, ISSN: 0013-5194

Journal article

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