619 results found
Petrov Z, Zaykov PG, Cardoso JMP, et al., 2013, An Aspect-Oriented Approach for Designing Safety-Critical Systems, IEEE Aerospace Conference, Publisher: IEEE, ISSN: 1095-323X
Kurek M, Becker T, Luk W, 2013, Parametric Optimization of Reconfigurable Designs Using Machine Learning, 9th International Applied Reconfigurable Computing Symposium (ARC), Publisher: SPRINGER-VERLAG BERLIN, Pages: 134-145, ISSN: 0302-9743
Chau TCP, Niu X, Eele A, et al., 2013, Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications, 9th International Applied Reconfigurable Computing Symposium (ARC), Publisher: SPRINGER-VERLAG BERLIN, Pages: 1-12, ISSN: 0302-9743
Niu X, Coutinho JGF, Luk W, 2013, A SCALABLE DESIGN APPROACH FOR STENCIL COMPUTATION ON RECONFIGURABLE CLUSTERS, 23rd International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Guo C, Luk W, 2013, ACCELERATING MAXIMUM LIKELIHOOD ESTIMATION FOR HAWKES POINT PROCESSES, 23rd International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Liu Q, Ma Y, Wang Y, et al., 2013, RALP: Reconvergence-Aware Layer Partitioning For 3D FPGAs, International Conference on Reconfigurable Computing and FPGAs (ReConFig), Publisher: IEEE, ISSN: 2325-6532
Gan L, Fu H, Luk W, et al., 2013, ACCELERATING SOLVERS FOR GLOBAL ATMOSPHERIC EQUATIONS THROUGH MIXED-PRECISION DATA FLOWENGINE, 23rd International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Todman T, Luk W, 2013, RUNTIME ASSERTIONS AND EXCEPTIONS FOR STREAMING SYSTEMS, 23rd International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Gan L, Fu H, Luk W, et al., 2013, Global Atmospheric Simulation on a Reconfigurable Platform, 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 230-230
Eele A, Maciejowski J, Chau T, et al., 2013, Parallelisation of sequential Monte Carlo for real-time control in air traffic management, Pages: 4859-4864, ISSN: 0191-2216
This paper presents the parallelisation of a Sequential Monte Carlo algorithm, and the associated changes required when applied to the problem of conflict resolution and aircraft trajectory control in air traffic management. The target problem is non-linear constrained, non-convex and multi-agent. The new method is shown to have a 98.5% computational time saving over that of a previous sequential implementation, with no degradation in path quality. The computation saving is enough to allow real-time implementation. © 2013 IEEE.
Niu X, Chau TCP, Jin Q, et al., 2013, Automating elimination of idle functions by run-time reconfiguration, 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 97-104
Eele A, Maciejowski J, Chau T, et al., 2013, Parallelisation of Sequential Monte Carlo for Real-Time Control in Air Traffic Management, 52nd IEEE Annual Conference on Decision and Control (CDC), Publisher: IEEE, Pages: 4853-4858, ISSN: 0743-1546
Grigoras P, Niu X, Coutinho JGF, et al., 2013, Aspect Driven Compilation for Dataflow Designs, IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Publisher: IEEE, Pages: 18-25, ISSN: 2160-0511
Cattaneo R, Niu X, Pilato C, et al., 2013, A Framework for Effective Exploitation of Partial Reconfiguration in Dataflow Computing, 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), Publisher: IEEE
Arram J, Luk W, Jiang P, 2013, ReconfigurACable Filtered Acceleration of Short Read AlignmentAC, 12th International Conference on Field-Programmable Technology (FPT), Publisher: IEEE, Pages: 438-441
Denholm S, Inouet H, Takenaka T, et al., 2013, Application-Specific Customisation of Market Data Feed Arbitration, 12th International Conference on Field-Programmable Technology (FPT), Publisher: IEEE, Pages: 322-325
Niu X, Coutinho JGF, Wang Y, et al., 2013, Computing nodes in reconfigurable clusters are occupied and released by applications during their, 12th International Conference on Field-Programmable Technology (FPT), Publisher: IEEE, Pages: 214-221
Arram J, Tsoi KH, Luk W, et al., 2013, Reconfigurable Acceleration of Short Read Mapping, 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 210-217
Guo C, Luk W, 2013, Accelerating HAC Estimation for Multivariate Time Series, IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Publisher: IEEE, Pages: 42-49, ISSN: 2160-0511
Chau TCP, Kwok K-W, Chow GCT, et al., 2013, Acceleration of Real-time Proximity Query for Dynamic Active Constraints, 12th International Conference on Field-Programmable Technology (FPT), Publisher: IEEE, Pages: 206-213
Inggs G, Thomas D, Luk W, 2013, A Heterogeneous Computing framework for Computational Finance, 42nd Annual International Conference on Parallel Processing (ICPP), Publisher: IEEE, Pages: 688-697, ISSN: 0190-3918
Ruan H, Huang X, Fu H, et al., 2013, An FPGA-Based Data Flow Engine For Gaussian Copula Model, 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 218-225
Thomas DB, Luk W, 2013, Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol: PP, Pages: 1-1-1-1, ISSN: 1063-8210
Niu X, Chau TCP, Jin Q, et al., 2013, Automating resource optimisation in reconfigurable design (abstract only)., Publisher: ACM, Pages: 275-275
Ng N, Yoshida N, Luk W, 2013, Scalable Session Programming for Heterogeneous High-Performance Systems, Publisher: Springer, Pages: 82-98
Betkaoui B, Wang Y, Thomas DB, et al., 2012, Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study, Pages: 99-104
This paper proposes a highly parallel and scalable reconfigurable design for the All-Pairs Shortest-Paths (APSP) algorithm for very sparse networks. Our work is motivated by a computationally intensive bioinformatics application that employs this memory-latency bound algorithm. The proposed design methodology takes advantage of distributed on-chip memory resources of modern FPGAs to reduce accesses to high-latency off-chip memories. We develop design optimisations that yield different FPGA configurations which are selected at run time based on the input graph data. Using human brain network data, we are able to achieve performance results superior to those from multi-core CPU and GPU, while attaining linear scaling over the number of processors introduced. Our FPGA-based APSP design is over 10 times faster than a quad-core CPU implementation and 2-5 times faster than an AMD Cypress GPU implementation. © 2012 IEEE.
Chau TCP, Luk W, Cheung PYK, et al., 2012, Adaptive sequential Monte Carlo approach for real-time applications, Pages: 527-530
This paper presents an adaptive Sequential Monte Carlo approach for real-time applications. Sequential Monte Carlo method is employed to estimate the states of dynamic systems using weighted particles. The proposed approach reduces the run-time computation complexity by adapting the size of the particle set. Multiple processing elements on FPGAs are dynamically allocated for improved energy efficiency without violating real-time constraints. A robot localisation application is developed based on the proposed approach. Compared to a non-adaptive implementation, the dynamic energy consumption is reduced by up to 70% without affecting the quality of solutions. © 2012 IEEE.
Jin Q, Becker T, Luk W, et al., 2012, Optimising explicit finite difference option pricing for dynamic constant reconfiguration, Pages: 165-172
This paper demonstrates a novel optimisation methodology to adjust stencil based numerical procedures from the algorithm level, so as to reduce not only the amount of hardware resource consumption per kernel but also the amount of computation required to achieve desired result accuracy, when mapping the algorithm to reconfigurable hardware using dynamic constant reconfiguration. As a result, less area is needed to support run-time reconfiguration, and less computational steps are required in the numerical procedure to obtain a result with given error tolerance. We analyse one thousand fixed point implementations on a Virtex-6 XC6VLX760 FPGA for randomly generated option pricing problems, which are representative of industrial computation. When comparing optimised implementations to the un-optimised ones, the reconfiguration area upper bound is reduced by 22%; the average number of computational steps is reduced by 23%; and the area-computation-time product is reduced by 40%; while the numerical errors of the results are kept below the error tolerant level used in industry. © 2012 IEEE.
Niu X, Jin Q, Luk W, et al., 2012, Exploiting run-time reconfiguration in stencil computation, Pages: 173-180
Stencil computation is computationally intensive and required by many applications. This paper proposes an approach to exploit run-time reconfigurability of field-programmable accelerators for stencil computation. System throughput is optimized by partitioning, analysing and scheduling tasks in applications to remove idle functions. To evaluate the proposed approach, Reverse Time Migration (RTM), a high performance application, is developed. Our optimized runtime reconfigurable solution, which targets a Virtex-6 FPGA in a Maxeler MAX3424A system, can achieves an improved throughput of 102.8 GFlop/s, up to two orders of magnitude faster than the CPU reference designs, 1.59 times faster than the best published GPU and FPGA results, and 1.45 times faster than an optimized static implementation. © 2012 IEEE.
Todman T, Luk W, 2012, Verification of streaming designs by combining symbolic simulation and equivalence checking, Pages: 203-208
As design complexity grows, verification becomes a bottleneck in design development and implementation. This paper describes a novel approach for verifying reconfigurable streaming designs, based on symbolic simulation and equivalence checking. Compared with numerical simulation, symbolic simulation provides a more informative way of showing a design behaved as expected; equivalence checking enables automatic checking of equivalence of symbolic expressions. Our approach has been implemented for designs targeting Maxeler technologies, using an easy-to-use symbolic simulator and the Yices equivalence checker, together with other facilities such as an output combiner to support an automated verification flow. Several benchmarks including, including one-dimensional convolution and finite difference computation, are used to evaluate the proposed approach. © 2012 IEEE.
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