611 results found
Chau T, Burovskiy P, Flynn M, et al., 2017, Advances in Dataflow Systems, ADVANCES IN COMPUTERS, VOL 106, Editors: Hurson, Milutinovic, Publisher: ELSEVIER ACADEMIC PRESS INC, Pages: 21-62, ISBN: 978-0-12-812230-3
Fu H, He C, Luk W, et al., 2017, A Nanosecond-level Hybrid Table Design for Financial Market Data Generators, 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 227-234
Zhao R, Niu X, Wu Y, et al., 2017, Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms, 13th International Symposium on Applied Reconfigurable Computing (ARC), Publisher: SPRINGER INTERNATIONAL PUBLISHING AG, Pages: 255-267, ISSN: 0302-9743
Funie A-I, Guo L, Niu X, et al., 2017, Custom Framework for Run-Time Trading Strategies, 13th International Symposium on Applied Reconfigurable Computing (ARC), Publisher: SPRINGER INTERNATIONAL PUBLISHING AG, Pages: 154-167, ISSN: 0302-9743
Grigoras P, Burovskiy P, Arram J, et al., 2017, dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs, 13th International Symposium on Applied Reconfigurable Computing (ARC), Publisher: SPRINGER INTERNATIONAL PUBLISHING AG, Pages: 299-310, ISSN: 0302-9743
Li T, Heinis T, Luk W, 2017, ADvaNCE - Efficient and Scalable Approximate Density-Based Clustering Based on Hashing, INFORMATICA, Vol: 28, Pages: 105-130, ISSN: 0868-4952
Gan L, Fu H, Mencer O, et al., 2017, Data Flow Computing in Geoscience Applications, CREATIVITY IN COMPUTING AND DATAFLOW SUPERCOMPUTING, Editors: Hurson, Milutinovic, Publisher: ELSEVIER ACADEMIC PRESS INC, Pages: 125-158, ISBN: 978-0-12-811955-6
Inggs G, Thomas DB, Luk W, 2017, A Domain Specific Approach to High Performance Heterogeneous Computing, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, Vol: 28, Pages: 2-15, ISSN: 1045-9219
Zhao R, Todman T, Luk W, et al., 2017, DeepPump: Multi-Pumping Deep Neural Networks, 28th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Publisher: IEEE, Pages: 206-206, ISSN: 2160-0511
Fu H, He C, Ruan H, et al., 2017, Accelerating Financial Market Server through Hybrid List Design, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Publisher: ASSOC COMPUTING MACHINERY, Pages: 289-290
Todman T, Luk W, 2017, In-Circuit Assertions and Exceptions for Reconfigurable Hardware Design., Provably Correct Systems, Editors: Hinchey, Bowen, Olderog, Publisher: Springer, Pages: 265-281, ISBN: 978-3-319-48627-7
Gan L, Fu H, Mencer O, et al., 2017, Chapter Four - Data Flow Computing in Geoscience Applications., Advances in Computers, Vol: 104, Pages: 125-158
Chau TCP, Burovskiy P, Flynn MJ, et al., 2017, Chapter Two - Advances in Dataflow Systems., Advances in Computers, Vol: 105, Pages: 21-62
Hmid SN, Coutinho JGF, Luk W, 2016, A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution, ACM SIGARCH Computer Architecture News, Vol: 43, Pages: 40-45, ISSN: 0163-5964
Ma Y, Zhang C, Luk W, 2016, Hybrid two-stage HW/SW partitioning algorithm for dynamic partial reconfigurable FPGAs, Qinghua Daxue Xuebao/Journal of Tsinghua University, Vol: 56, ISSN: 1000-0054
© 2016, Press of Tsinghua University. All right reserved. More and more hardware platforms are providing dynamic partial reconfiguration; thus, traditional hardware/software partitioning algorithms are no longer applicable. Some studies have analyzed the dynamic partial reconfiguration as mixed-integer linear programming (MILP) models to get solutions. However, the MILP models are slow and can only handle small problems. This paper uses heuristic algorithms to determine the status of some critical tasks to reduce the scale of the MILP problem for large problems. Tests show that this method is about 200 times faster with the same solution quality as the traditional mathematical programming method.
Cardoso JMP, Coutinho JGF, Carvalho T, et al., 2016, Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach, SOFTWARE-PRACTICE & EXPERIENCE, Vol: 46, Pages: 251-287, ISSN: 0038-0644
Cheung K, Schultz SR, Luk W, 2016, NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors, FRONTIERS IN NEUROSCIENCE, Vol: 9, ISSN: 1662-453X
Li T, Heinis T, Luk W, 2016, Hashing-based approximate DBSCAN, Pages: 31-45, ISSN: 0302-9743
© Springer International Publishing Switzerland 2016. Analyzing massive amounts of data and extracting value from it has become key across different disciplines. As the amounts of data grow rapidly, however, current approaches for data analysis struggle. This is particularly true for clustering algorithms where distance calculations between pairs of points dominate overall time. Crucial to the data analysis and clustering process, however, is that it is rarely straightforward. Instead, parameters need to be determined through several iterations. Entirely accurate results are thus rarely needed and instead we can sacrifice precision of the final result to accelerate the computation. In this paper we develop ADvaNCE, a new approach to approximating DBSCAN. ADvaNCE uses two measures to reduce distance calculation overhead: (1) locality sensitive hashing to approximate and speed up distance calculations and (2) representative point selection to reduce the number of distance calculations. Our experiments show that our approach is in general one order of magnitude faster (at most 30x in our experiments) than the state of the art.
Stroobandt D, Varbanescu AL, Ciobanu CB, et al., 2016, EXTRA: Towards the Exploitation of eXascale Technology for Reconfigurable Architectures, 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Publisher: IEEE
Grigoras P, Burovskiy P, Luk W, et al., 2016, Optimising Sparse Matrix Vector Multiplication for Large Scale FEM problems on FPGA, 26th International Conference on Field-Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Lindsey B, Leslie M, Luk W, 2016, A Domain Specific Language for Accelerated Multilevel Monte Carlo Simulations, 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Publisher: IEEE, Pages: 99-106, ISSN: 1063-6862
Yu T, Feng B, Stillwell M, et al., 2016, Relation-Oriented Resource Allocation for Multi-Accelerator Systems, 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Publisher: IEEE, Pages: 243-244, ISSN: 1063-6862
Zhao W, Fu H, Luk W, et al., 2016, F-CNN: An FPGA-based Framework for Training Convolutional Neural Networks, 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Publisher: IEEE, Pages: 107-114, ISSN: 1063-6862
Kurek M, Becker T, Guo C, et al., 2016, Self-aware hardware acceleration of financial applications on a heterogeneous cluster, Natural Computing Series, Pages: 241-260
© Springer International Publishing Switzerland 2016. This chapter describes self-awareness in four financial applications. We apply some of the design patterns of Chapter 5 and techniques of Chapter 7. We describe three applications briefly, highlighting the links to self-awareness and self-expression. The applications are (i) a hybrid genetic programming and particle swarm optimisation approach for high-frequency trading, with fitness function evaluation accelerated by FPGA; (ii) an adaptive point process model for currency trading, accelerated by FPGA hardware; (iii) an adaptive line arbitrator synthesising high-reliability and low-latency feeds from redundant data feeds (A/B feeds) using FPGA hardware. Finally, we describe in more detail a generic optimisation approach for reconfigurable designs automating design optimisation, using reconfigurable hardware to speed up the optimisation process, applied to applications including a quadrature-based financial application. In each application, the hardware-accelerated self-aware approaches give significant benefits: up to 55× speedup for hardware-accelerated design optimisation compared to software hill climbing.
Niu X, Todman T, Luk W, 2016, Self-adaptive hardware acceleration on a heterogeneous cluster, Natural Computing Series, Pages: 167-192
© Springer International Publishing Switzerland 2016. Building a cluster of computers is a common technique to significantly improve the throughput of computationally intensive applications. Communication networks connect hundreds to thousands of compute nodes to form a cluster system, where a parallelisable application workload is distributed into the compute nodes. Theoretically, heterogeneous clusters with various types of processing units are more efficient than homogeneous clusters, since some types of processing units perform better than others on certain applications. A heterogeneous cluster can achieve better cluster performance by adapting cluster configurations to assign applications to processing elements that fit well with the applications. In this chapter we describe how to build a heterogeneous cluster that can adapt to application requirements. Section 9.1 provides an overview of heterogeneous computing. Section 9.2 presents the commonly used hardware and software architectures of heterogeneous clusters. Section 9.3 discusses the use of self-awareness and self-adaptivity in two runtime scenarios of a heterogeneous cluster, and Section 9.4 presents the experimental results. Finally, Section 9.5 discusses approaches to formally verify the developed applications.
Shao S, Mencer O, Luk W, 2016, Dataflow Design for Optimal Incremental SVM Training, 15th International Conference on Field-Programmable Technology (FPT), Publisher: IEEE, Pages: 197-200
Zhou H, Niu X, Yuan J, et al., 2016, Connect On the Fly: Enhancing and Prototyping of Cycle-Reconfigurable Modules, 26th International Conference on Field-Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Grigoras P, Burovskiy P, Luk W, 2016, CASK - Open-Source Custom Architectures for Sparse Kernels, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Publisher: ASSOC COMPUTING MACHINERY, Pages: 179-184
Kurek M, Deisenroth MP, Luk W, et al., 2016, Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs, 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 84-87
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