Imperial College London

ProfessorWayneLuk

Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Hung:2014:10.1109/FPL.2014.6927497,
author = {Hung, E and Todman, T and Luk, W},
doi = {10.1109/FPL.2014.6927497},
title = {Transparent insertion of latency-oblivious logic onto FPGAs},
url = {http://dx.doi.org/10.1109/FPL.2014.6927497},
year = {2014}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - © 2014 Technical University of Munich (TUM). We present an approach for inserting latency-oblivious functionality into pre-existing FPGA circuits transparently. To ensure transparency - that such modifications do not affect the design's maximum clock frequency - we insert any additional logic post place-and-route, using only the spare resources that were not consumed by the pre-existing circuit. The typical challenge with adding new functionality into existing circuits incrementally is that spare FPGA resources to host this functionality must be located close to the input signals that it requires, in order to minimise the impact of routing delays. In congested designs, however, such co-location is often not possible. We overcome this challenge by using flow techniques to pipeline and route signals from where they originate, potentially in a region of high resource congestion, into a region of low congestion capable of hosting new circuitry, at the expense of latency. We demonstrate and evaluate our approach by augmenting realistic designs with self-monitoring circuitry, which is not sensitive to latency. We report results on circuits operating over 200MHz and show that our insertions have no impact on timing, are 2-4 times faster than compile-time insertion, and incur only a small power overhead.
AU - Hung,E
AU - Todman,T
AU - Luk,W
DO - 10.1109/FPL.2014.6927497
PY - 2014///
TI - Transparent insertion of latency-oblivious logic onto FPGAs
UR - http://dx.doi.org/10.1109/FPL.2014.6927497
UR - http://hdl.handle.net/10044/1/23842
ER -