Imperial College London

ProfessorWayneLuk

Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Hung:2015:10.1145/2684746.2689075,
author = {Hung, E and Levine, JM and Stott, E and Constantinides, GA and Luk, W},
doi = {10.1145/2684746.2689075},
pages = {56--65},
title = {Delay-bounded routing for shadow registers},
url = {http://dx.doi.org/10.1145/2684746.2689075},
year = {2015}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - The on-chip timing behaviour of synchronous circuits can be quantified at run-time by adding shadow registers, which allow designers to sample the most critical paths of a circuit at a different point in time than the user register would normally. In order to sample these paths precisely, the path skew between the user and the shadow register must be tightly controlled and consistent across all paths that are shadowed. Unlike a custom IC, FPGAs contain prefabricated resources from which composing an arbitrary routing delay is not trivial. This paper presents a method for inserting shadow registers with a minimum skew bound, whilst also reducing the maximum skew. To preserve circuit timing, we apply this to FPGA circuits post place-and-route, using only the spare resources left behind. We find that our techniques can achieve an average STA reported delay bound of ±200ps on a Xilinx device despite incomplete timing information, and achieve <1ps accuracy against our own delay model.
AU - Hung,E
AU - Levine,JM
AU - Stott,E
AU - Constantinides,GA
AU - Luk,W
DO - 10.1145/2684746.2689075
EP - 65
PY - 2015///
SP - 56
TI - Delay-bounded routing for shadow registers
UR - http://dx.doi.org/10.1145/2684746.2689075
UR - http://hdl.handle.net/10044/1/21638
ER -