Imperial College London


Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering



+44 (0)20 7594 8313w.luk Website




434Huxley BuildingSouth Kensington Campus






BibTex format

author = {Niu, X and Luk, W and Wang, Y},
doi = {10.1145/2684746.2689076},
pages = {74--83},
title = {EURECA: On-chip configuration generation for effective dynamic data access},
url = {},
year = {2015}

RIS format (EndNote, RefMan)

AB - © Copyright ACM. This paper describes Effective Utilities for Run-timE Configuration Adaptation (EURECA), a novel memory architecture for supporting effective dynamic data access in reconfigurable devices. EURECA exploits on-chip configuration generation to reconfigure active connections in such devices cycle by cycle. When integrated into a baseline architecture based on the Virtex-6 SX475T, the EURECA memory architecture introduces small area, delay and power overhead. Three benchmark applications are developed with the proposed architecture targeting social networking (Memcached), scientific computing (sparse matrix-vector multiplication), and in-memory database (large-scale sorting). Compared with conventional static designs, up to 14.9 times reduction in area, 2.2 times reduction in critical-path delay, and 32.1 times reduction in area-delay product are achieved.
AU - Niu,X
AU - Luk,W
AU - Wang,Y
DO - 10.1145/2684746.2689076
EP - 83
PY - 2015///
SP - 74
TI - EURECA: On-chip configuration generation for effective dynamic data access
UR -
ER -