Imperial College London

ProfessorWayneLuk

Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Niu:2016:10.1109/FPL.2016.7577359,
author = {Niu, X and Ng, N and Yuki, T and Wang, S and Yoshida, N and Luk, W},
doi = {10.1109/FPL.2016.7577359},
publisher = {IEEE},
title = {EURECA Compilation: Automatic Optimisation of Cycle-Reconfigurable Circuits},
url = {http://dx.doi.org/10.1109/FPL.2016.7577359},
year = {2016}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AU - Niu,X
AU - Ng,N
AU - Yuki,T
AU - Wang,S
AU - Yoshida,N
AU - Luk,W
DO - 10.1109/FPL.2016.7577359
PB - IEEE
PY - 2016///
SN - 1946-1488
TI - EURECA Compilation: Automatic Optimisation of Cycle-Reconfigurable Circuits
UR - http://dx.doi.org/10.1109/FPL.2016.7577359
UR - http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000386610400061&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202
UR - http://hdl.handle.net/10044/1/34334
ER -