Imperial College London

ProfessorWayneLuk

Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Grigoras:2016:10.1109/FPL.2016.7577352,
author = {Grigoras, P and Burovskiy, P and Luk, W and Sherwin, S},
doi = {10.1109/FPL.2016.7577352},
title = {Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA},
url = {http://dx.doi.org/10.1109/FPL.2016.7577352},
year = {2016}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - Sparse Matrix Vector multiplication (SpMV) is an important kernel in many scientific applications. In this work we propose an architecture and an automated customisation method to detect and optimise the architecture for block diagonal sparse matrices. We evaluate the proposed approach in the context of the spectral/hp Finite Element Method, using the local matrix assembly approach. This problem leads to a large sparse system of linear equations with block diagonal matrix which is typically solved using an iterative method such as the Preconditioned Conjugate Gradient. The efficiency of the proposed architecture combined with the effectiveness of the proposed customisation method reduces BRAM resource utilisation by as much as 10 times, while achieving identical throughput with existing state of the art designs and requiring minimal development effort from the end user. In the context of the Finite Element Method, our approach enables the solution of larger problems than previously possible, enabling the applicability of FPGAs to more interesting HPC problems.
AU - Grigoras,P
AU - Burovskiy,P
AU - Luk,W
AU - Sherwin,S
DO - 10.1109/FPL.2016.7577352
PY - 2016///
SN - 1946-1488
TI - Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA
UR - http://dx.doi.org/10.1109/FPL.2016.7577352
UR - http://hdl.handle.net/10044/1/42864
ER -