Imperial College London


Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering



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BibTex format

author = {Fu, H and He, C and Luk, W and Li, W and Yang, G},
publisher = {IEEE},
title = {A nanosecond-level hybrid table design for financial market data generators},
url = {},

RIS format (EndNote, RefMan)

AB - This paper proposes a hybrid sorted table designfor minimizing electronic trading latency, with three maincontributions. First, a hierarchical sorted table with twolevels, a fast cache table in reconfigurable hardware storingmegabytes of data items and a master table in software storinggigabytes of data items. Second, a full set of operations,including insertion, deletion, selection and sorting, for thehybrid table with latency in a few cycles. Third, an on-demand synchronization scheme between the cache table andthe master table. An implementation has been developed thattargets an FPGA-based network card in the environment of theChina Financial Futures Exchange (CFFEX) which sustains 1-10Gb/s bandwidth with latency of 400 to 700 nanoseconds,providing an 80- to 125-fold latency reduction compared to afully optimized CPU-based solution, and a 2.2-fold reductionover an existing FPGA-based solution.
AU - Fu,H
AU - He,C
AU - Luk,W
AU - Li,W
AU - Yang,G
TI - A nanosecond-level hybrid table design for financial market data generators
UR -
ER -