Imperial College London


Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering



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BibTex format

author = {Ng, HC and Liu, S and Luk, W},
doi = {10.1145/3174243.3174247},
pages = {189--198},
title = {ADAM: Automated design analysis and merging for speeding up FPGA development},
url = {},
year = {2018}

RIS format (EndNote, RefMan)

AB - © 2018 Association for Computing Machinery. This paper introduces ADAM, an approach for merging multiple FPGA designs into a single hardware design, so that multiple place- and-route tasks can be replaced by a single task to speed up functional evaluation of designs, especially during the development process. ADAM has three key elements. First, a novel approximate maximum common subgraph detection algorithm with linear time complexity to maximize sharing of resources in the merged design. Second, a prototype tool implementing this common subgraph detection algorithm for dataflow graphs derived from Verilog designs; this tool would also generate the appropriate control circuits to enable selection of the original designs at runtime. Third, a comprehensive analysis of compilation time versus degree of similarity to identify the optimized user parameters for the proposed approach. Experimental results show that ADAM can reduce compilation time by around 5 times when each design is 95% similar to the others, and the compilation time is reduced from 1 hour to 10 minutes in the case of binomial filters.
AU - Ng,HC
AU - Liu,S
AU - Luk,W
DO - 10.1145/3174243.3174247
EP - 198
PY - 2018///
SP - 189
TI - ADAM: Automated design analysis and merging for speeding up FPGA development
UR -
UR -
ER -