611 results found
, 2018, Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control, ISSN: 1063-6862
© 2018 IEEE. Reinforcement Learning (RL) is an area of machine learning in which an agent interacts with the environment by making sequential decisions. The agent receives reward from the environment based on how good the decisions are and tries to find an optimal decision-making policy that maximises its longterm cumulative reward. This paper presents a novel approach which has showon promise in applying accelerated simulation of RL policy training to automating the control of a real robot arm for specific applications. The approach has two steps. First, design space exploration techniques are developed to enhance performance of an FPGA accelerator for RL policy training based on Trust Region Policy Optimisation (TRPO), which results in a 43% speed improvement over a previous FPGA implementation, while achieving 4.65 times speed up against deep learning libraries running on GPU and 19.29 times speed up against CPU. Second, the trained RL policy is transferred to a real robot arm. Our experiments show that the trained arm can successfully reach to and pick up predefined objects, demonstrating the feasibility of our approach.
© 2018 IEEE. Hardware accelerators are attractive targets for running scientific simulations due to their power efficiency. Since, large software simulations can take person years to develop, it is often impractical to use hardware acceleration, which requires significantly more development effort and expertise than software development. We present the design and implementation of a proof-of-concept compiler toolchain which enables rapid prototyping of hardware finite difference solvers for partial differential equations, generated from a high-level domain specific language. Multiple fields, grid staggering and non-linear terms are supported. We demonstrate that our approach is practical by generating and evaluating hardware designs derived from the heat and simplified shallow water equations.
Fan X, Wu D, Cao W, et al., 2018, Stream Processing Dual-Track CGRA for Object Inference, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol: 26, Pages: 1098-1111, ISSN: 1063-8210
Papaphilippou P, Luk W, Accelerating database systems using FPGAs: A survey, The International Conference on Field-Programmable Logic and Applications (FPL), 2018, Publisher: IEEE
Database systems are key to a variety of applications, and FPGA-based accelerators have shown promise in supporting high-performance database systems. This survey presents a systematic review of research relating to accelerating analytical database systems using FPGAs. The review includes studies of database acceleration frameworks and accelerator implementations for various database operators. Finally, the survey includes some promising future technologies and discussion on the challenges to be addressed by the future research in this area.
Lee K-H, Fu KCD, Guo Z, et al., 2018, MR Safe Robotic Manipulator for MRI-Guided Intracardiac Catheterization, IEEE-ASME TRANSACTIONS ON MECHATRONICS, Vol: 23, Pages: 586-595, ISSN: 1083-4435
, 2018, ADAM: Automated design analysis and merging for speeding up FPGA development, Pages: 189-198
© 2018 Association for Computing Machinery. This paper introduces ADAM, an approach for merging multiple FPGA designs into a single hardware design, so that multiple place- and-route tasks can be replaced by a single task to speed up functional evaluation of designs, especially during the development process. ADAM has three key elements. First, a novel approximate maximum common subgraph detection algorithm with linear time complexity to maximize sharing of resources in the merged design. Second, a prototype tool implementing this common subgraph detection algorithm for dataflow graphs derived from Verilog designs; this tool would also generate the appropriate control circuits to enable selection of the original designs at runtime. Third, a comprehensive analysis of compilation time versus degree of similarity to identify the optimized user parameters for the proposed approach. Experimental results show that ADAM can reduce compilation time by around 5 times when each design is 95% similar to the others, and the compilation time is reduced from 1 hour to 10 minutes in the case of binomial filters.
Zhao R, Liu S, Ng H-C, et al., 2018, Hardware Compilation of Deep Neural Networks: An Overview, 29th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Publisher: IEEE, Pages: 120-127, ISSN: 2160-0511
Funie A-I, Grigoras P, Burovskiy P, et al., 2018, Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies, JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, Vol: 90, Pages: 39-52, ISSN: 1939-8018
Zhao R, Niu X, Luk W, 2018, Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only)., Publisher: ACM, Pages: 285-285
Zhao R, Ng H-C, Luk W, et al., 2018, Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA.
Liu S, Niu X, Luk W, 2018, A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only., Publisher: ACM, Pages: 293-293
Russell FP, Duben PD, Niu X, et al., 2017, Exploiting the chaotic behaviour of atmospheric models with reconfigurable architectures, COMPUTER PHYSICS COMMUNICATIONS, Vol: 221, Pages: 160-173, ISSN: 0010-4655
He C, Fu H, Guo C, et al., 2017, A Fully-Pipelined Hardware Design for Gaussian Mixture Models, IEEE TRANSACTIONS ON COMPUTERS, Vol: 66, Pages: 1837-1850, ISSN: 0018-9340
Cooper B, Girdlestone S, Burovskiy P, et al., 2017, Quantum Chemistry in Dataflow: Density-Fitting MP2, JOURNAL OF CHEMICAL THEORY AND COMPUTATION, Vol: 13, Pages: 5265-5272, ISSN: 1549-9618
Yan J, Yuan J, Leong PHW, et al., 2017, Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol: 25, Pages: 2842-2855, ISSN: 1063-8210
© 2017 IEEE. This paper presents an approach to enhance the performance of machine learning applications based on hardware acceleration. This approach is based on parameterised architectures designed for Convolutional Neural Network (CNN) and Support Vector Machine (SVM), and the associated design flow common to both. This approach is illustrated by two case studies including object detection and satellite data analysis. The potential of the proposed approach is presented.
Gan L, Fu H, Luk W, et al., 2017, Solving Mesoscale Atmospheric Dynamics Using a Reconfigurable Dataflow Architecture, IEEE MICRO, Vol: 37, Pages: 40-50, ISSN: 0272-1732
Hung E, Todman T, Luk W, 2017, Transparent In-Circuit Assertions for FPGAs, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol: 36, Pages: 1193-1202, ISSN: 0278-0070
Arram J, Kaplan T, Luk W, et al., 2017, Leveraging FPGAs for Accelerating Short Read Alignment, IEEE-ACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS, Vol: 14, Pages: 668-677, ISSN: 1545-5963
Burovskiy P, Grigoras P, Sherwin S, et al., 2017, Efficient Assembly for High-Order Unstructured FEM Meshes (FPL 2015), ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, Vol: 10, ISSN: 1936-7406
Leong PHW, Amano H, Anderson J, et al., 2017, The First 25 Years of the FPL Conference: Significant Papers, ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, Vol: 10, ISSN: 1936-7406
Fan H, Niu X, Liu Q, et al., 2017, F-C3D: FPGA-based 3-Dimensional Convolutional Neural Network, 27th International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Targett JS, Duben P, Luk W, 2017, Validating Optimisations for Chaotic Simulations, 27th International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Shao S, Luk W, 2017, Customised Pearlmutter Propagation: A Hardware Architecture for Trust Region Policy Optimisation, 27th International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
He C, Fu H, Luk W, et al., 2017, Exploring the Potential of Reconfigurable Platforms for Order Book Update, 27th International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Voss N, Bacis M, Mencer O, et al., 2017, Convolutional Neural Networks on Dataflow Engines, 35th IEEE International Conference on Computer Design (ICCD), Publisher: IEEE, Pages: 435-438, ISSN: 1063-6404
Li W, He C, Fu H, et al., 2017, An FPGA-based tree crown detection approach for remote sensing images, 16th IEEE International Conference on Field-Programmable Technology (ICFPT), Publisher: IEEE, Pages: 231-234
Ng H-C, Liu S, Luk W, 2017, Reconfigurable Acceleration of Genetic Sequence Alignment: A Survey of Two Decades of Efforts, 27th International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Lee K-H, Leong MCW, Chow MCK, et al., 2017, FEM-based Soft Robotic Control Framework for Intracavitary Navigation, IEEE International Conference on Real-time Computing and Robotics (RCAR), Publisher: IEEE, Pages: 11-16
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