Imperial College London
Professor Wayne Luk

ProfessorWayneLuk

Faculty of Engineering, Department of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Zhou:2016:10.1109/FPL.2016.7577332,
author = {Zhou, H and Niu, X and Yuan, J and Wang, L and Luk, W},
doi = {10.1109/FPL.2016.7577332},
publisher = {IEEE},
title = {Connect on the fly: enhancing and prototyping of cycle-reconfigurable modules},
url = {http://dx.doi.org/10.1109/FPL.2016.7577332},
year = {2016}
}
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RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - This paper introduces cycle-reconfigurable modulesthat   enhance   FPGA   architectures   with   efficient   support   fordynamic data accesses: data accesses with accessed data size andlocation  known  only  at  runtime.  The  proposed  module  adoptsnew  reconfiguration  strategies  based  ondynamic FIFOs,dynamiccaches,   anddynamic  shared  memoriesto   significantly   reduceconfiguration  generation  and  routing  complexity.  We  developa  prototype  FPGA  chip  with  the  proposed  cycle-reconfigurablemodule in the SMIC 130-nm technology. The integrated moduletakes  less  than  the  chip  area  of  39  CLBs,  and  reconfiguresthousands of runtime connections in 1.2 ns. Applications for large-scale   sorting,   sparse   matrix-vector   multiplication,   and   Mem-cached  are  developed.  The  proposed  modules  enable  1.4  and11  times  reductions  in  area-delay  product  compared  with  thoseapplications  mapped  to  previous  architectures  and  conventionalFPGAs.
AU  - Zhou,H
AU  - Niu,X
AU  - Yuan,J
AU  - Wang,L
AU  - Luk,W
DO  - 10.1109/FPL.2016.7577332
PB  - IEEE
PY  - 2016///
TI  - Connect on the fly: enhancing and prototyping of cycle-reconfigurable modules
UR  - http://dx.doi.org/10.1109/FPL.2016.7577332
UR  - https://ieeexplore.ieee.org/document/7577332
UR  - http://hdl.handle.net/10044/1/34335
ER  -
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