Imperial College London

ProfessorWayneLuk

Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@article{Yan:2017:10.1109/TVLSI.2017.2713527,
author = {Yan, J and Yuan, J and Leong, PHW and Luk, W and Wang, L},
doi = {10.1109/TVLSI.2017.2713527},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
pages = {2842--2855},
title = {Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis},
url = {http://dx.doi.org/10.1109/TVLSI.2017.2713527},
volume = {25},
year = {2017}
}

RIS format (EndNote, RefMan)

TY  - JOUR
AB - As the density of field-programmable gate arrays continues to increase, the size of configuration bitstreams grows accordingly. Compression techniques can reduce memory size and save external memory bandwidth. To accelerate the configuration process and reduce the software startup time, four open-source lossless compression decoders developed using high-level synthesis techniques are presented. Moreover, in order to balance the objectives of compression ratio, decompression throughput, and hardware resource overhead, various improvements and optimizations are proposed. Full bitstreams and software binaries have been collected as a benchmark, and 33 partial bitstreams have also been developed and integrated into the benchmark. Evaluations of the synthesizable compression decoders are demonstrated on a Xilinx ZC706 board, showing higher decompression throughput than those of the existing lossless compression decoders using our benchmark. The proposed decoders can reduce software startup time by up to 31.23% in embedded systems and 69.83% reduction of reconfiguration time for partial reconfigurable systems.
AU - Yan,J
AU - Yuan,J
AU - Leong,PHW
AU - Luk,W
AU - Wang,L
DO - 10.1109/TVLSI.2017.2713527
EP - 2855
PY - 2017///
SN - 1063-8210
SP - 2842
TI - Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis
T2 - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UR - http://dx.doi.org/10.1109/TVLSI.2017.2713527
UR - http://hdl.handle.net/10044/1/56369
VL - 25
ER -