16 results found
Liu Y, Luan S, Williams I, et al., A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput, IEEE Transactions on Biomedical Circuits and Systems, Pages: 1-12, ISSN: 1932-4545
Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.
Gao C, Ghoreishizadeh S, Liu Y, et al., 2017, On-chip ID generation for multi-node implantable devices using SA-PUF, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681
This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 m CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.
Ghoreishizadeh SS, Haci D, Liu Y, et al., 2017, A 4-Wire Interface SoC for Shared Multi- Implant Power Transfer and Full-duplex Communication, 8th IEEE Latin American Symposium on Circuits & Systems (LASCAS), Publisher: IEEE
Haci D, Liu Y, Constandinou TG, 2017, 32-channel ultra-low-noise arbitrary signal generation platform for biopotential emulation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701
This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10kHz bandwidth, 110dB dynamic range and uV-level output noise.
Liu Y, L Pereira J, Constandinou T, 2017, Event-driven processing for hardware-efficient neural spike sorting., J Neural Eng
The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope for large-scale integration of neural recording systems. In such systems the hardware resource, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can here provide a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous time level-crossing sampling for efficient data representation and subsequent spike processing. We first compare signals (using synthetic neural datasets) that are encoded using this technique against conventional sampling. It is observed that considerably lower data rates are achievable when utilising 7 bits or less to represent the signals, whilst maintaining the signal fidelity. We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. The proposed method is implemented in a low power FPGA platform to demonstrate the hardware viability. Results obtained using both MATLAB and reconfigurable logic (FPGA) hardware indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware cost.
Maslik M, Liu Y, Lande TS, et al., 2017, A charge-based ultra-low power continuous-time ADC for data driven neural spike processing, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1420-1423
The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75uW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4uW. The circuit has been implemented in a commercially available 0.35um CMOS technology with core occupying a footprint of 0.12 sq.mm
Liu Y, Pereira JL, Constandinou TG, 2016, Clockless Continuous-Time Neural Spike Sorting: Method, Implementation and Evaluation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 538-541, ISSN: 0271-4302
Luan S, Liu Y, Williams I, et al., 2016, An Event-Driven SoC for Neural Recording, 12th IEEE Biomedical Circuits and Systems Conference (BioCAS), Publisher: IEEE, Pages: 404-407, ISSN: 2163-4025
Ramezani R, Dehkhoda F, Soltan A, et al., 2016, An Optrode with built-in self-diagnostic and fracture sensor for cortical brain stimulation, 12th IEEE Biomedical Circuits and Systems Conference (BioCAS), Publisher: IEEE, Pages: 392-395, ISSN: 2163-4025
Williams I, Rapeaux A, Liu Y, et al., 2016, A 32-Ch. Bidirectional Neural/EMG Interface with on-Chip Spike Detection for Sensorimotor Feedback, 12th IEEE Biomedical Circuits and Systems Conference (BioCAS), Publisher: IEEE, Pages: 528-531, ISSN: 2163-4025
Dehkhoda F, Soltan A, Ramezani R, et al., 2015, Smart Optrode for Neural Stimulation and Sensing, 2015 IEEE SENSORS, Publisher: IEEE, Pages: 1965-1968, ISSN: 1930-0395
Zhao H, Dehkhoda F, Ramezani R, et al., 2015, A CMOS-based Neural Implantable Optrode for Optogenetic Stimulation and Electrical Recording, 11th IEEE Annual Biomedical Circuits and Systems Conference (BioCAS), Publisher: IEEE, Pages: 286-289, ISSN: 2163-4025
Barsakcioglu DY, Liu Y, Bhunjun P, et al., 2014, An Analogue Front-End Model for Developing Neural Spike Sorting Systems, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, Vol: 8, Pages: 216-227, ISSN: 1932-4545
Liu Y, Georgiou P, Prodromakis T, et al., 2011, An Extended CMOS ISFET Model Incorporating the Physical Design Geometry and the Effects on Performance and Offset Variation, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol: 58, Pages: 4414-4422, ISSN: 0018-9383
Prodromakis T, Liu Y, Toumazou C, 2011, A Low-Cost Disposable Chemical Sensing Platform Based on Discrete Components, IEEE ELECTRON DEVICE LETTERS, Vol: 32, Pages: 417-419, ISSN: 0741-3106
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