Publications
142 results found
Krali E, Fobelets K, Durrani Z, 2014, Seebeck coefficient in Si nanowires and single-electron effects, Mico and Nano Engineering (MNE) 2014, Lausanne
Rasool K, Rafiq MA, Durrani ZAK, 2014, Tailoring transport and dielectric properties by surface passivation of silicon nanowires with Polyacrylic acid/TiO<sub>2</sub> nanoparticles composite, MICROELECTRONIC ENGINEERING, Vol: 119, Pages: 141-145, ISSN: 0167-9317
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- Citations: 7
Durrani ZAK, 2014, Seebeck coefficient of one electron, Journal of Applied Physics, Vol: 115, ISSN: 0021-8979
The Seebeck coefficient of one electron, driven thermally into a semiconductor single-electron box, is investigated theoretically. With a finite temperature difference ΔT between the source and charging island, a single electron can charge the island in equilibrium, directly generating a Seebeck effect. Seebeck coefficients for small and finite ΔT are calculated and a thermally driven Coulomb staircase is predicted. Single-electron Seebeck oscillations occur with increasing ΔT, as one electron at a time charges the box. A method is proposed for experimental verification of these effects.
Krali E, Durrani ZAK, 2013, Seebeck coefficient in silicon nanowire arrays (vol 102, 143102, 2013), APPLIED PHYSICS LETTERS, Vol: 103, ISSN: 0003-6951
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- Citations: 1
Wang C, Jones M, Durrani Z, 2013, Nanowire single–electron transistors with varying gate layouts, MIcro and Nano Engineering (MNE) 2013, London
Krali E, Li C, Fobelets K, et al., 2013, Seebeck coefficient in silicon nanowire arrays, Micro and Nanoengineering (MNE2013), London
Rasool K, Rafiq A, Durrani Z, 2013, Tailoring transport and dielectric properties by surface passivation of silicon nanowires with polyacrlylic acid/ TiO2 nanoparticle composite, Micro and Nano Engineering (MNE) 2013, London
Krali E, Durrani ZAK, 2013, Seebeck coefficient in silicon nanowire arrays, Applied Physics Letters, Vol: 102, Pages: 143102-143102-4
We measure the Seebeck coefficient S in large arrays of lightly doped n-Si nanowires (SiNWs). Our samples consist of ~10^7 NWs in parallel, forming a “bulk” nano-structured material. We find that the phonon drag component of S, a manifestation of electron-phonon scattering in the sample, is heavily suppressed due to surface scattering, and that there is a “universal” temperature dependence for S. Furthermore, at room temperature, S is enhanced in the arrays by up to ~3 times in comparison to bulk Si.
Durrani ZAK, Jones M, Kaestner M, et al., 2013, Scanning Probe Lithography approach for beyond CMOS devices, SPIE Advanced Lithography Conference 2013
Durrani Z, Kaestner M, Hofer M, et al., 2013, Scanning probe lithography for electronics at the 5 nm scale, Publisher: SPIE
Krali E, Li C, Fobelets K, et al., 2013, Seebeck coefficient in silicon nanowire arrays, Japan Society for the Promotion of Science (JSPS) Meeting (2012)
Durrani ZAK, 2012, Electrifying Possibilities
The electronics Industry is close to an exciting breakthrough using single electrons
Durrani ZAK, 2012, Nanoscale single-electron and quantum dot devices for 'beyond-CMOS' application, Nano-S&T 2012
Krali E, Durrani ZAK, 2012, Seebeck coefficient in silicon nanowire arrays, Micro and Nanoengineering (MNE) 2012
Ahmad M, Rasool K, Rafiq MA, et al., 2012, Effect of incorporation of zinc sulfide nanoparticles on carrier transport in silicon nanowires, PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES, Vol: 45, Pages: 201-206, ISSN: 1386-9477
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- Citations: 12
Xu B, Li C, Myronov M, et al., 2012, Si <inf>1-x</inf>Ge <inf>x</inf> nanowire arrays for thermoelectric power generation, Pages: 76-77
Thermoelectricity offers an excellent clean energy generation opportunity and has attracted renewed attention in the last few decades. The low conversion efficiency and high costs currently limit its practical application. Much effort is still needed to enhance its efficiency and reduce its cost. Nanostructures have been proven to greatly enhance the thermoelectric figure of merit (ZT) because of increased phonon scattering at the interfaces. It has been demonstrated that single Si nanowires (NWs) exhibit a 60 times higher ZT than Si bulk. Meanwhile, SiGe alloys can also reduce the thermal conductivity via alloy scattering without deteriorating the other performance parameters such as Seebeck coefficient, S and electrical conductivity, . SiGe NWs thus promise to offer even better thermoelectric performance than Si. In this work, we will show our recent research results on the fabrication and thermoelectric characterisation of SiGe nanowire arrays (NWAs). The NWAs are arrays of millions of parallel upstanding NWs attached to Si bulk, rather than single NWs as studied before. A Seebeck coefficient of S 1.1 mV/K is measured for the SiGe NWAs/Si bulk composite and is independent of Ge fraction, consistent with the theoretically expected value. The temperature drop across the SiGe NWA is consistently larger than across a similar Si NWA, indicating reduced thermal conductivity of the SiGe NWs.The use of SiGe improves the output power with a factor of 8 in the bulk TEG configuration. The use of SiGe NWAs in the p-leg only, increases the output power by a factor of 5 in comparison with the Si NWA TEG. These improvements are due to the reduction of the thermal conductance of the SiGe NWs and the reduction of the electrical contact resistance of the SiGe-based wires while the Seebeck coefficient remains unaffected © 2012 IEEE.
Rasool K, Rafiq MA, Li CB, et al., 2012, Enhanced electrical and dielectric properties of polymer covered silicon nanowire arrays, Applied Physics Letters, Vol: 101, Pages: 023114-1-023114-4
We investigate DC and AC electrical characteristics of 40 lm long p-type silicon nanowire(SiNW) arrays, prepared by metal assisted chemical etching and filled with polyacrylic acid (PAA). PAA diluted to different concentrations with deionized (DI) water is incorporated into the arrays in three steps, yielding polymer filling to the bottom of the arrays. DC and AC electrical measurements show that PAA reduces the array resistance. The AC conductivity increases up to ~1000 times, and the real part of the overall dielectric constant (e') by ~100. We attribute these effects to the formation of acceptor-like states at nanowire/polymer interface.
Fobelets K, Durrani ZAK, Ding PW, et al., 2012, Electrical transport in polymer covered Si nanowires, IEEE Transactions on nanotechnology, Vol: 11, Pages: 661-665, ISSN: 1536-125X
The influence of polymer layers wrapped around ntype Si nanowires on their electrical characteristics is investigated. The nanowires are fabricated via metal induced excessive oxidation and dissolution of Si, and have a diameter of ~350 nm. Single wires are covered by various polymer layers. The polymers used, are both insulating (PMMA, PE, PS, and PEO) and semiconducting (PEDOT:PSS). Four-point probe measurements are used to measure the conductivity changes of single nanowires. The nanowire resistivity increases with PE and PMMA coverage but decreases with PEO coverage. The changes are attributed to carrier exchange between the polymer and nanowire. The measurements also confirm active electron trapping with PE coverage that is not observed with the other polymers.
Rafiq MA, Masubuchi K, Durrani ZAK, et al., 2012, High ON/OFF ratio and multimode transport in silicon nanochains field effect transistors, APPLIED PHYSICS LETTERS, Vol: 100, ISSN: 0003-6951
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- Citations: 5
Rafiq MA, Masubuchi K, Durrani ZAK, et al., 2012, Conduction Bottleneck in Silicon Nanochain Single Electron Transistors Operating at Room Temperature, Japanese Journal of Applied Physics, Vol: 51, Pages: 025202-025202-6
Li CB, Xu B, Durrani ZAK, et al., 2012, Thermoelectric characteristics of SiGe nanowire arrays as a function of Ge concentration, 9th European Conference on Thermoelectrics (ECT), Publisher: AMER INST PHYSICS, Pages: 417-420, ISSN: 0094-243X
Li CB, Fobelets K, Durrani ZAK, 2011, Study of two-step electroless etched Si nanowire arrays, 2010 Int. Conf. Nano Science and Technology
Li CB, Fobelets K, Tymieniecki MS, et al., 2011, Bunch-free Electroless-etched Si Nanowire Array, 218th ECS Meeting
Li C, Fobelets K, Jalal SNS, et al., 2011, Influence of chemical modification on the electrical properties of Si nanowire arrays, International Conference on Materials Science and Engineering Applications, Publisher: TRANS TECH PUBLICATIONS LTD, Pages: 1331-1335, ISSN: 1022-6680
Durrani ZAK, Zaremba-Tymieniecki M, 2011, Schottky-barrier modulation of silicon nanowire field-effect transistors prepared by metal-assisted chemical etching, Micro and Nanoengineering 2011
Zaremba-Tymieniecki M, Durrani ZAK, 2011, Schottky-barrier lowering in silicon nanowire field-effect transistors prepared by metal-assisted chemical etching, Applied Physics Letters, Vol: 98, Pages: 102113-102113-3
We investigate the influence of Schottky barrier lowering in Si nanowire field-effect transistors,using nanowires prepared by metal-assisted chemical etching. The experimental electrical characteristics of a p-channel transistor are modeled using thermionic emission of holes across the reverse-biased source Schottky barrier. This barrier is lowered by the image-force potential, and by the electric field generated by both source-drain and gate voltages. The gate voltage lowers the barrier height directly and in addition, modulates the effect of the source-drain voltage on barrierlowering.
Ng A, Li C, Fobelets K, et al., 2010, Fabrication and characterisation of nanowire/polymer composite arrays, 2010 MRS Fall Exhibition
Zaremba-Tymieniecki M, Durrani ZAK, Li C, et al., 2010, Field-effect transistors fabricated using silicon nanowires prepared by metal-catalysed wet-chemical etching, Micro and Nanoengineering 2010
Zaremba-Tymieniecki M, Li C, Fobelets K, et al., 2010, Field-effect transistors using silicon nanowiresprepared by electroless chemical etching, IEEE Electron Device Letters, Vol: 31, Pages: 860-862, ISSN: 0741-3106
Silicon nanowires, prepared by electroless chemical etching, are used to fabricate dual-gate field-effect transistors. The diameters of the nanowires vary from 40–300 nm, with a maximum aspect ratio of ˜3000. Titanium silicide contacts are fabricated on single nanowires. An aluminium top-gate, combined with a back-gate, forms a dual-gate transistor. In an n-channeldevice with a nanowire diameter of ˜70 nm, the output characteristics show current saturation, with a maximum current of ˜100 nA. A drain-source threshold voltage exists for current flow,controlled by the gate voltage, and assists in device turn-off. The ON/OFF current ratio is ˜3000, and the subthreshold swing is ˜780 mV/decade.
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