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  • Journal article
    Maslik M, Liu Y, Lande TS, Constandinou TGet al., 2018,

    Continuous-time acquisition of biosignals using a charge-based ADC topology

    , IEEE Transactions on Biomedical Circuits and Systems, Vol: 12, Pages: 471-482, ISSN: 1932-4545

    This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of ≈5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35 μm CMOS technology occupying a compact footprint of 0.12 mm 2 . Silicon verified measurements demonstrate an 8-bit resolution and a 4 kHz bandwidth with static power consumption of 3.75 μW from a 1.5 V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39 pJ energy per conversion.
  • Journal article
    Ramezani R, Liu Y, Dehkhoda F, Soltan A, Haci D, Zhao H, Hazra A, Cunningham M, Firfilionis D, Jackson A, Constandinou TG, Degenaar Pet al., 2018,

    On-probe neural interface ASIC for combined electrical recording and optogenetic stimulation

    , IEEE Transactions on Biomedical Circuits and Systems, Vol: 12, Pages: 576-588, ISSN: 1932-4545

    Neuromodulation technologies are progressing from pacemaking and sensory operations to full closed-loop control. In particular, optogenetics—the genetic modification of light sensitivity into neural tissue allows for simultaneous optical stimulation and electronic recording. This paper presents a neural interface application-specified integrated circuit (ASIC) for intelligent optoelectronic probes. The architecture is designed to enable simultaneous optical neural stimulation and electronic recording. It provides four low noise (2.08 μVrms) recording channels optimized for recording local field potentials (LFPs) (0.1–300 Hz bandwidth, ± 5 mV range, sampled 10-bit@4 kHz), which are more stable for chronic applications. For stimulation, it provides six independently addressable optical driver circuits, which can provide both intensity (8-bit resolution across a 1.1 mA range) and pulse-width modulation for high-radiance light emitting diodes (LEDs). The system includes a fully digital interface using a serial peripheral interface (SPI) protocol to allow for use with embedded controllers. The SPI interface is embedded within a finite state machine (FSM), which implements a command interpreter that can send out LFP data whilst receiving instructions to control LED emission. The circuit has been implemented in a commercially available 0.35 μm CMOS technology occupying a 1.95 mm × 1.10 mm footprint for mounting onto the head of a silicon probe. Measured results are given for a variety of bench-top, in vitro and in vivo experiments, quantifying system performance and also demonstrating concurrent recording and stimulation within relevant experimental models.
  • Conference paper
    Leene L, Maslik M, Feng P, Szostak K, Mazza F, Constandinou TGet al., 2018,

    Autonomous SoC for neural local field potential recording in mm-scale wireless implants

    , IEEE International Symposium on Circuits and Systems, Publisher: IEEE, Pages: 1-5, ISSN: 2379-447X

    Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency when observing neural activity over a long period of time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing local field potentials (LFPs) only, chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a ΔΣ based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 μm CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.77μVrms. The resulting electronics has a core area of 2.1 mm2 and a power budget of 92 μW
  • Journal article
    Liu Y, Pereira J, Constandinou TG, 2018,

    Event-driven processing for hardware-efficient neural spike sorting

    , Journal of Neural Engineering, Vol: 15, Pages: 1-14, ISSN: 1741-2552

    Objective. The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing. Approach. (1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability. Main results. It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources. Significance. By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.
  • Book chapter
    Williams I, Leene L, Constandinou TG, 2018,

    Next Generation Neural Interface Electronics

    , Circuit Design Considerations for Implantable Devices, Editors: Cong, Publisher: River Publishers, Pages: 141-178, ISBN: 978-87-93519-86-2
  • Patent
    Cavuto ML, Winter AG, Constandinou T, 2018,

    Apparatus and Method for Inserting Electrode-based Probes into Biological Tissue
  • Journal article
    Liu Y, Luan S, Williams I, Rapeaux A, Constandinou TGet al., 2017,

    A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput

    , IEEE Transactions on Biomedical Circuits and Systems, Vol: 11, Pages: 1344-1355, ISSN: 1932-4545

    Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.
  • Journal article
    Szostak K, Grand L, Constandinou TG, 2017,

    Neural interfaces for intracortical recording: requirements, fabrication methods, and characteristics

    , Frontiers in Neuroscience, Vol: 11, ISSN: 1662-4548

    Implantable neural interfaces for central nervous system research have been designed with wire, polymer or micromachining technologies over the past 70 years. Research on biocompatible materials, ideal probe shapes and insertion methods has resulted in building more and more capable neural interfaces. Although the trend is promising, the long-term reliability of such devices has not yet met the required criteria for chronic human application. The performance of neural interfaces in chronic settings often degrades due to foreign body response to the implant that is initiated by the surgical procedure, and related to the probe structure, and material properties used in fabricating the neural interface. In this review, we identify the key requirements for neural interfaces for intracortical recording, describe the three different types of probes- microwire, micromachined and polymer-based probes; their materials, fabrication methods, and discuss their characteristics and related challenges.
  • Journal article
    Leene L, Constandinou TG, 2017,

    Time domain processing techniques using ring oscillator-based filter structures

    , IEEE Transactions on Circuits and Systems Part 1: Regular Papers, Vol: 64, Pages: 3003-3012, ISSN: 1549-8328

    The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth- order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure- of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst addition- ally offering direct integration with digital systems.
  • Conference paper
    Mifsud A, Haci D, Ghoreishizadeh S, Liu Y, Constandinou TGet al., 2017,

    Adaptive Power Regulation and Data Delivery for Multi-Module Implants

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 584-587
  • Conference paper
    Feng P, Constandinou TG, Yeon P, Ghovanloo Met al., 2017,

    Millimeter-Scale Integrated and Wirewound Coils for Powering Implantable Neural Microsystems

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 488-491
  • Conference paper
    Szostak K, Mazza F, Maslik M, Feng P, Leene L, Constandinou TGet al., 2017,

    Microwire-CMOS Integration of mm-Scale Neural Probes for Chronic Local Field Potential Recording

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 492-495
  • Conference paper
    Luo J, Firfilionis D, Ramezani R, Dehkhoda F, Soltan A, Degenaar P, Liu Y, Constandinou TGet al., 2017,

    Live demonstration: a closed-loop cortical brain implant for optogenetic curing epilepsy

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 169-169
  • Conference paper
    De Marcellis A, Palange E, Faccio M, Stanchieri GDP, Constandinou TGet al., 2017,

    A 250Mbps 24pJ/bit UWB-inspired Optical Communication System for Bioimplants

    , Turin, Italy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 132-135
  • Conference paper
    Maslik M, Liu Y, Lande TS, Constandinou TGet al., 2017,

    A charge-based ultra-low power continuous-time ADC for data driven neural spike processing

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1420-1423

    The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75uW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4uW. The circuit has been implemented in a commercially available 0.35um CMOS technology with core occupying a footprint of 0.12 sq.mm
  • Conference paper
    Haci D, Liu Y, Constandinou TG, 2017,

    32-channel ultra-low-noise arbitrary signal generation platform for biopotential emulation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701

    This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10kHz bandwidth, 110dB dynamic range and uV-level output noise.
  • Conference paper
    Gao C, Ghoreishizadeh S, Liu Y, Constandinou TGet al., 2017,

    On-chip ID generation for multi-node implantable devices using SA-PUF

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681

    This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 m CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.
  • Conference paper
    Guven O, Eftekhar A, Kindt W, Constandinou TGet al., 2017,

    Low-power real-time ECG baseline wander removal: hardware implementation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1571-1574

    This paper presents a hardware realisation of a novel ECG baseline drift removal that preserves the ECG signal integrity. The microcontroller implementation detects the fiducial markers of the ECG signal and the baseline wander estimation is achieved through a weighted piecewise linear interpolation. This estimated drift is then removed to recover a “clean” ECG signal without significantly distorting the ST segment. Experimental results using real data from the MIT-BIH Arrhythmia Database (recording 100 and 101) with added baseline wander (BWM1) from the MIT-BIH Noise Stress Database show an average root mean square error of 34.3uV (mean), 30.4u V (median) and 18.4uV (standard deviation) per heart beat.
  • Conference paper
    Dávila-Montero S, Barsakcioglu DY, Jackson A, Constandinou TG, Mason AJet al., 2017,

    Real-time clustering algorithm that adapts to dynamic changes in neural recordings

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 690-693

    This work presents a computationally efficient real-time adaptive clustering algorithm that recognizes and adapts to dynamic changes observed in neural recordings. The algorithm consists of an off-line training phase that determines initial cluster positions, and an on-line operation phase that continuously tracks drifts in clusters and periodically verifies acute changes in cluster composition. Analysis of chronic recordings from non-human primates shows that adaptive clustering achieves an improvement of 14% in classification accuracy and demonstrates an ability to recognize acute changes with 78% accuracy, with up to 29% computational efficiency compared to the state-of-the-art. The presented algorithm is suitable for long-term chronic monitoring of neural activity in various applications such as neuroscience research and control of neural prosthetics and assistive devices.
  • Conference paper
    Leene L, Constandinou TG, 2017,

    A 0.5V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2619-2622, ISSN: 2379-447X

    This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nanometre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which isnot well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked ΔΣ behavior which is useful on-chip characterizationand interfacing with synchronous systems. A 0.5V instrumentation system is implemented using a 65nm TSMC technology to realize a highly compact footprint that is 0.006mm2 in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 Vrms input referred noise for the given 810nW total system power budget corresponding to an NEF of 1.64.

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