CMS Tracker Upgrade
To maximise the discovery potential of the LHC beyond 2020, the machine will require a series of upgrades so that it can reach its ultimate luminosity and deliver a total 3000fb-1 of integrated luminosity in its lifetime. The high-luminosity (HL-LHC) conditions will however have serious implications for the CMS detector and especially its tracking systems. The increased particle fluence will necessitate the complete replacement of the existing silicon strip tracker before 2022 due to accumulated radiation damage of the sensors and potentially intolerable detector occupancies. The replacement tracker must be more granular, leading to increased power consumption and hence cooling requirements and material. In addition, the first level trigger (L1) rate must for the first time include tracking information so that CMS can retain sensitivity across all physics searches and is able to improve on measurements of Higgs while operating under challenging high pileup conditions.
Triggering using stacked sensors
Readout of the full tracker every 25ns would constitute an aggregate bandwidth requirement of ~500Tbps. This would be impossible to implement using cutting edge technology without seriously compromising the design and physics performance of the tracker. Instead, CMS are looking to novel methods of selecting the most interesting tracking data on-detector, before readout, in order to reduce the bandwidth requirements. Collisions at the LHC produce a large number of low momentum particles that make up a significant fraction of hit data generated by the tracker. Charged particles with transverse momentum pT < 0.7GeV/c are considered uninteresting for the purposes of triggering since they fail to reach the outer sub-detectors due to the bending power of the 4T magnetic field. By correlating hits between closely spaced (“stacked”) sensors, this low pT background can be rejected by only passing hits that lie with O(100um) of each other in the bending plane. These high pT candidate hits or stubs can then be transferred off-detector and passed to a fast track finder or to some trigger decision logic at L1.
CMS Binary Chip (CBC)
The CBC2 is a 254-channel binary unsparsified prototype ASIC fabricated in 130nm CMOS designed for readout of stacked silicon strip sensors in the outer regions of an upgraded tracker. It succeeds a previous 128-channel version which achieves ≈800e RMS noise for a total power of less than 300μW/channel. A sensor can be DC or AC coupled to the CBC front-end preamplifier, and the chip can be selected to read either electrons or holes. The analogue pulse shape has an overall peaking time of 20 ns following the post-amplification stage with a gain of ~50 mV/fC. Channel to channel DC shifts can be corrected via programmable offsets before the pulse is compared against a global programmable threshold at the comparator, and sampled into pipeline memory at 40MHz. The pipeline RAM is 256 samples deep, which corresponds to a 6.4us latency for the L1 trigger. The CBC2 has been specifically designed as a flip chip ASIC for C4 bump-bonding to a dedicated hybrid.
The CBC2 is also capable of identifying hits from high pT tracks in stacked strip (2S) modules. Clustering logic aggregates consecutive hit strips while automatically rejecting wide clusters. During correlation, for every valid cluster on the inner sensor, the logic looks for a hit within a configurable coincidence window on the outer sensor. If a hit is present within this window, the inner strip is considered a valid stub and a flag is raised. The CBC2 forms a vital part of the 2S prototype module testing programme and is currently under evaluation alongside the first prototype modules. A third iteration of the CBC is planned for submission in 2014.
The picture (left) shows the design for a stacked module currently being proposed for the outer regions of the tracker (r > 500mm). The two strip sensors are wire-bonded to either side of a hybrid and are then read out by 16 bump-bonded CBCs. The module is designed to be lightweight and to rely on commercial technology for the electrical interconnects which, due to the dual sensor design, is already challenging. The high density hybrid substrate which handles the sensor pitch adaption, vias the signals through from the lower sensor to the CBC and routes the CBC control and data lines is already being prototyped and the first versions are being qualified. The stub and triggered data from the CBCs are then formatted and managed by a concentrator ASIC before transmission off-detector via a bidirectional multi-gigabit (GBT) link over optical fibre.
The pT threshold for stub selection can be adjusted by changing the width of the coincidence window in the upper layer (programmable in CBC2) and the separation between silicon sensors. The optimal sensor separation varies in the range 1mm-4mm in the barrel and 1mm-5mm in the endcaps, depending on the pT cut required and the radius of the layer/disk.