Citation

BibTex format

@inproceedings{Que:2023:10.1109/FPL57034.2022.00057,
author = {Que, Z and Loo, M and Fan, H and Pierini, M and Tapper, A and Luk, W},
doi = {10.1109/FPL57034.2022.00057},
pages = {327--333},
publisher = {IEEE},
title = {Optimizing graph Neural Networks for jet tagging in particle physics on FPGAs},
url = {http://dx.doi.org/10.1109/FPL57034.2022.00057},
year = {2023}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - This work proposes a novel reconfigurable architecture for reducing the latency of JEDI-net, a Graph NeuralNetwork (GNN) based algorithm for jet tagging in particlephysics, which achieves state-of-the-art accuracy. AcceleratingJEDI-net is challenging since it requires low latency to deploythe network for event selection at the CERN Large HadronCollider. This paper proposes an outer-product based matrixmultiplication approach customized for GNN-based JEDI-net,which increases data spatial locality and reduces design latency.It is further enhanced by code transformation with strengthreduction which exploits sparsity patterns and binary adjacencymatrices to increase hardware efficiency while reducing latency.In addition, a customizable template for this architecture hasbeen designed and open-sourced, which enables the generationof low-latency FPGA designs with efficient resource utilizationusing high-level synthesis tools. Evaluation results show that ourFPGA implementation is up to 9.5 times faster and consumes upto 6.5 times less power than a GPU implementation. Moreover,the throughput of our FPGA design is sufficiently high to enabledeployment of JEDI-net in a sub-microsecond, real-time collidertrigger system, enabling it to benefit from improved accuracy.
AU - Que,Z
AU - Loo,M
AU - Fan,H
AU - Pierini,M
AU - Tapper,A
AU - Luk,W
DO - 10.1109/FPL57034.2022.00057
EP - 333
PB - IEEE
PY - 2023///
SP - 327
TI - Optimizing graph Neural Networks for jet tagging in particle physics on FPGAs
UR - http://dx.doi.org/10.1109/FPL57034.2022.00057
UR - http://hdl.handle.net/10044/1/97854
ER -