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  • Conference paper
    Mirza KB, Luan S, Constandinou TG, 2012,

    Towards a Fully-Integrated Solution for Capacitor-Based Neural Stimulation

    , International Symposium on Circuits and Systems (ISCAS), ISSN: 0271-4302

    Charge-mode stimulation (ChgMS) is a relatively new method being explored in the field of electrical neural stimulation. One of the key challenges in such a system is to overcome charge sharing between the storage capacitor and the double layer capacitor in the Electrode-Electrolyte-Interface (EEI). In this work, this issue is overcome by using a second-generation negative current conveyor (CCII-) with low current tracking error. The level of charge sharing in the circuit is expressed by a new figure of merit (charge delivery efficiency) introduced in this paper. The proposed system has a maximum power efficiency of 76.6% and a total power consumption of 270uW per electrode for a target charge stimulus of 0.9nC. Crucially, the system achieves a minimum charge delivery efficiency of 98.22%.

  • Conference paper
    Williams I, Constandinou TG, 2012,

    An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis

    , International Symposium on Circuits and Systems (ISCAS), ISSN: 0271-4302

    This paper presents an energy-efficient neuralstimulator capable of providing charge-balanced asymmetric pulses. Power consumption is reduced by implementing a fully-integrated DC-DC converter that uses a reconfigurable switched capacitor topology to provide 4 output voltages for DynamicVoltage Scaling (DVS). DC conversion efficiencies of between 63% and 76% are achieved using integrated capacitances of under 1nF and the DVS approach offers power savings of up to 53.5%compared to the front end of a typical current controlled neural stimulator. Charge balancing is achieved to a low level of accuracy on a single pulse and a much higher accuracy over a series ofpulses. The method used is robust to process and component variation and does not require any initial or ongoing calibration. Monte-Carlo simulations indicate that the charge imbalance willbe less than 0.014% (at 3 sigma ) of charge delivered for a series of pulses. The circuit has been designed in a commercially-available0.18 m HV CMOS technology and requires a die areaof <0.5 sq. mm for a 16 channel implementation.

  • Conference paper
    Paraskevopoulou SE, Constandinou TG, 2012,

    An Ultra-Low-Power Front-End Neural Interface with Automatic Gain for Uncalibrated Monitoring

    , International Symposium on Circuits and Systems (ISCAS), ISSN: 0271-4302

    This paper presents a dynamic front-end towards achieving unsupervised single-neuron activity monitoring. By implementing at the front-end, an automatic gain control that is optimised for neural signal dynamics, subsequent processing can be achieved without the need for calibration. The system uses three amplification stages (low-noise first stage, variable-gain second stage and high-gain third stage), a tuneable high-pass filter, and a feedback loop to tune the variable gain. The circuit has been implemented in a commercially-available 0.18um CMOS technology with total power consumption between 1.79 and 1.95$uW$ The front-end achieves a variable gain from 52 to 86.4dB with 3kHz bandwidth and a high-pass filter that is tuneable from 100-300Hz. The input referred noise is 9.66uV with a total harmonic distortion of under 1%.

  • Conference paper
    Haaheim B, Constandinou TG, 2012,

    A Sub-1μW, 16kHz Current-Mode SAR-ADC for Neural Spike Recording

    , International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, ISSN: 0271-4302

    This paper presents an ultra-low-power 8-bit asynchronous current-mode (CM) successive approximation (SAR) analogue-to-digital converter (ADC) for single-neuron spike recording. The novel design exploits CM techniques to support operation at supply voltages down to 1.2V, consuming under500nA at 16kSamples/s. The design features easy scalability, and allows for a tuneable sampling frequency and dynamic range (DR). The circuit is designed in a commercially-available 0.18u mCMOS technology and occupies a chip area of 0.078 The system requires a single, post-fabrication current calibration supportedby on-chip circuitry to ensure robust operation through process and mismatch variations.

  • Patent
    Georgiou P, Prodromakis T, Constandinou TG, Toumazou Cet al., 2011,

    Sensor Array for Measuring Neural Activity

    A sensor system comprising a substrate and integrated onto the substrate an array (7) of sensor elements (1), each sensor element comprising one or more inductors (3), one or more electrochemical sensors (4), and one or more optical sensors (2). The system further comprising a controller configured in use to separately address each of the sensor elements (1) to drive the respective inductors and receive outputs of the respective sensors.

  • Journal article
    武藤 弘, Knopfel T, 2011,

    Engineering voltage-sensitive fluorescent protein and monitoring neuronal activities

    , Bio industry, Vol: 28, Pages: 18-25, ISSN: 0910-6545
  • Conference paper
    Paraskevopoulou S, Constandinou TG, 2011,

    A sub-1μW Neural Spike-Peak Detection and Spike-Count Rate Encoding Circuit

    , IEEE Biomedical Circuits and Systems (BioCAS) conference, Publisher: IEEE, Pages: 29-32

    In this paper we present a circuit for determining neural spike features such as peak occurrence, peak amplitude and spike count rate in continuous-time. The system achieves these functions concurrently and in real-time achieving an accuracy higher than a typical digital solution (constrained by a the sampling time and/or resolution). For an average spike rate of 50$spikes/s$ the system consumes 815nW designed in a commercially-available 0.18μm CMOS technology. The complete circuit core (excluding bondpads) occupies a total area of approximately 0.022mm²

  • Conference paper
    Luan S, Eftekhar A, Murphy O, Constandinou TGet al., 2011,

    Towards an Inductively Coupled Power/Data Link for Bondpad-Less Silicon Chips

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 7-10

    This paper explores the concept of developing a bondpad-less fullyintegrated inductive link for power/data transfer between a silicon chip and a PCB. A key feature of the implemented system is that it requires no off-chip components. The proposed chip uses a standard 0.35um process and occupies an area of 2.5 x 2.5 mm^2. 9mW power was designed to be obtained on-chip through 900MHz carrier wave. Binary Phase Shift Keying (BPSK) and Load shift keying (LSK) are used for the the PCB-to-chip and chip-to-PCB link respectively for half-duplex communication.

  • Conference paper
    Sole M, Sanni A, Vilches A, Toumazou C, Constandinou TGet al., 2011,

    A Bio-Implantable Platform for Inductive Data and Power Transfer with Integrated Battery Charging

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2605-2608

    This paper describes a mixed signal subsystem for the inductive transfer of power and data to a fully-implantable medical device. The design includes circuits for the inductive power recovery and energy storage (charging), in addition to data recovery and demodulation. The data link is used to upload (at a data rate of up to 180Kbps) calibration and configuration data to the implanted device and integrates both error detection and correction on the recovered bitstream. The system incorporates an implanted Li-Ion micro-battery with supporting charging hardware to provide an uninterrupted power supply for autonomous deployment. This is to provide continuous operation without the requirement for an externally worn unit and additionally ensures registry (i.e. patient calibration) settings are maintained. The circuit has been implemented in a commercially available 0.35um CMOS technology without requiring high-voltage device options.

  • Conference paper
    Constandinou TG, Georgiou P, Prodromakis T, Toumazou Cet al., 2010,

    A CMOS-based Lab-on-Chip Array for the Combined Magnetic Stimulation and Opto-Chemical Sensing of Neural Tissue

    , Berkeley, CA, 2010 12th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Publisher: IEEE, Pages: 1-6

    This paper presents a novel CMOS-based lab-on-chip platform for non-contact magnetic stimulation and recording of neural tissue. The proposed system is the first of its kind to integrate magnetic-stimulation and opto-chemical sensing in a single pixel, tesselated to form an 8 × 8 array. Fabricated in a commercially-available 0.35 ¿m CMOS technology, the system can be intrinsically used for both optical imaging and pH sensing and includes mechanisms for calibrating out sensor variation and mismatch. In addition to sensory acquisition via an integrated 10-bit ADC, a 64-instruction spatiotemporal pattern generator has been embedded within the array for driving the microscale magnetic neural stimulation. In this application the ISFET-based sensors are used to capacitively-couple neuronal charge in close proximity to the floating gate. Optical imaging hardware has also been embedded to provide topographic detail of the neural tissue.

  • Conference paper
    Eftekhar A, Paraskevopoulou S, Constandinou TG, 2010,

    Towards Next Generation Neural Interfaces: Optimizing Power, Bandwidth and Data Quality

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 122-125

    In this paper, we review the state-of-the-art in neural interface recording architectures. Through this we identify schemes which show the trade-off between data information quality (lossiness), computation (i.e. power and area requirements) and the number of channels. These trade-offs are then extended by considering the front-end amplifier bandwidth to also be a variable. We therefore explore the possibility of band-limiting the spectral content of recorded neural signals (to save power) and investigate the effect this has on subsequent processing (spike detection accuracy). We identify the spike detection method most robust to such signals, optimize the threshold levels and modify this to exploit such a strategy.

  • Conference paper
    Eftekhar A, Constandinou TG, Abbruzzese D, Woods V, Triantis IF, Drakakis EM, Toumazou Cet al., 2009,

    A Programmable Neural Interface for Investigating Arbitrary Stimulation Strategies

    , 14th Annual International FES Society Conference
  • Conference paper
    Constandinou TG, Georgiou J, Toumazou C, 2009,

    A Neural Implant ASIC for the Restoration of Balance in Individuals with Vestibular Dysfunction

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 641-644
  • Journal article
    Constandinou TG, Georgiou J, 2008,

    A Micropower Arcsine Circuit for Tilt Processing

    , Electronics Letters, Vol: 44, Pages: 1336-1338, ISSN: 0013-5194

    This letter describes an analogue circuit for producing an arcsine transfer based on a differential pair with source degeneration. The application uses this circuit to post-process an accelerometer signal by normalising with respect to the gravitational acceleration vector to extract inclination. Using diode-connected MOS devices operating in weak inversion, the appropriate trigonometric function, i.e. an arcsine, has been realised to compute tilt. The hardware has been implemented in AMS 0.35μm 2P4M CMOS technology.

  • Journal article
    Constandinou TG, Georgiou J, Toumazou C, 2008,

    A Partial-Current-Steering Biphasic Stimulation Driver for Vestibular Prostheses

    , IEEE Transactions on Biomedical Circuits and Systems, Vol: 2, Pages: 106-113, ISSN: 1932-4545

    This paper describes a novel partial-current-steering stimulation circuit for implantable vestibular prostheses. The drive hardware momentarily delivers a charge-balanced asymmetric stimulus to a dummy load before steering towards the stimulation electrodes. In this fashion, power is conserved while still gaining from the benefits of current steering. The circuit has been designed to be digitally programmable as part of an implantable vestibular prosthesis. The hardware has been implemented in AMS 0.35μm 2P4M CMOS technology.

  • Journal article
    Constandinou TG, Georgiou J, Toumazou C, 2008,

    Towards an Integrated, Fully-Implantable Vestibular Prosthesis for Balance Restoration

    , Journal of Advances in Science and Technology, Vol: 57, Pages: 210-215

    Neuroprosthetics is a relatively new topic but it has already shown its potential. Since the application of this science, it has already significantly improved the quality of life of over 60,000 individuals who previously suffered from severely impaired hearing or total deafness. Today, through use of cochlear implants, children born totally deaf can enjoy going to regular schools and communicating normally. Individuals suffering from dizziness and balance disorders can also benefit from the progress made in cochlear prosthetics. The inner ear's vestibular system provides cues about self-motion and help stabilise vision during movement. Damage to this system can result in dizziness, imbalance, blurred vision and instability in locomotion, a leading cause of death in the elderly. We propose a hybrid CMOS/MEMS platform for bypassing a dysfunctional pathway in individuals that suffer from balance-related disorders. Combining MEMS-based inertia sensing with CMOS-based neural monitoring and processing electronics, this prosthesis aims to deliver a corrective artificial stimulus to the vestibulocochlear (VIII) nerve. We describe a novel system outlining the architectural aspects and implementation methodology used in the design.

  • Conference paper
    Constandinou TG, Georgiou J, Toumazou C, 2008,

    A Fully-Integrated Semicircular Canal Processor for an Implantable Vestibular Prosthesis

    , IEEE International Conference on Electronics, Circuits and Systems (ICECS), Publisher: IEEE, Pages: 81-84
  • Conference paper
    Constandinou TG, Georgiou J, Toumazou C, 2008,

    A Partial-Current-Steering Biphasic Stimulation Driver for Neural Prostheses

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2506-2509
  • Journal article
    Constandinou TG, Georgiou J, 2008,

    Micro-Optoelectromechanical Tilt Sensor

    , Journal of Sensors, Pages: 1-7, ISSN: 1687-725X

    This paper presents a novel hybrid CMOS/MEMS tilt sensor with a 5∘ resolution over a 300∘ range. The device uses a MEMS-based semicircular mass suspended from a rigid body, projecting a shadow onto the CMOS-based optical sensor surface. A one-dimensional photodiode array arranged as a uniformly segmented ring is then used to determine the tilt angle by detecting the position of the semicircular mass. The complete sensor occupies an area of under 2.5 mm × 2.5 mm.

  • Journal article
    Lande TS, Constandinou TG, Burdett A, Toumazou Cet al., 2007,

    Running cross-correlation using bitstream processing

    , Electronics Letters, Vol: 43, Pages: 1181-1183, ISSN: 0013-5194

    A novel architecture for running cross-correlation and convolution using bitstream processing is proposed. The computationally intensive multiplications inherent in cross-correlation and convolution are replaced by simple logic operations (AND XOR) using bitstream representation. The reduced complexity enables compact and energy efficient silicon solutions suitable for small, portable devices such as wearable heartbeat detecting electronics embedded in the actual ECG patch.

  • Journal article
    Triantis IF, Woods V, Eftekhar A, Georgiou P, Constandinou TG, Drakakis EM, Toumazou Cet al., 2007,

    Advances in Neural Interfacing

    , IEEE Circuits and Systems Society Newsletter, Vol: 1
  • Conference paper
    Constandinou TG, Georgiou J, Doumanidis CC, Tournazou Cet al., 2007,

    Towards an Implantable vestibular prosthesis: The surgical challenges

    , 3rd International IEEE/EMBS Conference on Neural Engineering, Publisher: IEEE, Pages: 40-+
  • Conference paper
    Eftekhar A, Constandinou TG, Triantis IF, Toumazou C, Drakakis EMet al., 2007,

    Towards a Reconfigurable Sense-and-Stimulate Neural Interface Generating Biphasic Interleaved Stimulus

    , 3rd International IEEE/EMBS Conference on Neural Engineering (CNE), Publisher: IEEE, Pages: 438-441
  • Conference paper
    Li X, Constandinou TG, Eftekhar A, Georgiou P, Toumazou Cet al., 2007,

    Towards a bionic neural link for implantable prosthetics

    , IEEE EMBS Conference on Neural Engineering, Publisher: Institute of Electrical and Electronics Engineers (IEEE), Pages: 85-88
  • Conference paper
    Georgiou J, Constandinou TG, Toumazou C, 2007,

    A Micropower Cochlear Prosthesis System Demonstrator

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: Institute of Electrical and Electronics Engineers (IEEE), Pages: 1219-1219
  • Journal article
    Faisal AA, White JA, Laughlin SB,

    Supplemental Data Ion-Channel Noise Places Limits on the Miniaturization of the Brain’s Wiring

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