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  • Conference paper
    Rapeaux A, Brunton E, Nazarpour K, Constandinou TGet al., 2018,

    Preliminary study of time to recovery of rat sciatic nerve from high frequency alternating current nerve block

    , 40th International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Publisher: IEEE

    High-Frequency alternating current nerve block has great potential for neuromodulation-based therapies. However, no precise measurements have been made of the time needed for nerves to recover from block once the signal has been turned off. This study aims to characterise time to recoveryof the rat sciatic nerve after 30 seconds of block at varying amplitudes and frequencies. Experiments were carried out in-vivo to quantify recovery times and recovery completeness within 0.7s from the end of block. The sciatic nerve was blocked with an alternating square wave signal of amplitudeand frequency ranging from 2 to 9mA and 10 to 50 kHz respectively. To determine the recovery dynamics the nerve was stimulated at 100 Hz after cessation of the blocking stimulus. Electromyogram signals were measured from the gastrocnemius medialis and tibialis anterior muscles during trials as indicators of nerve function. This allowed for nerve recovery to bemeasured with a resolution of 10 ms. This resolution is much greater than previous measurements of nerve recovery in the literature. Times for the nerve to recover to a steady state of activity ranged from 20 to 430 milliseconds and final relative recovery activity at 0.7 seconds spanned 0.2 to 1 approximately. Higher blocking signal amplitudes increased recovery time and decreased recovery completeness. These results suggestthat blocking signal properties affect nerve recovery dynamics, which could help improve neuromodulation therapies and allow more precise comparison of results across studies using different blocking signal parameters.

  • Conference paper
    Szostak KM, Constandinou TG, 2018,

    Hermetic packaging for implantable microsystems: effectiveness of sequentially electroplated AuSn alloy

    , 40th International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Publisher: IEEE

    With modern microtechnology, there is an aggressive miniaturization of smart devices, despite an increasing level of integration and overall complexity. It is therefore becoming increasingly important to be achieve reliable, compact packaging. For implantable medical devices (IMDs), the package must additionally provide a high quality hermetic environmentto protect the device from the human body. For chip-scale devices, AuSn eutectic bonding offers the possibility of forming compact seals that achieve ultra-low permeability. A key feature is this can be achieved at process temperatures of below 350 C, therefore allowing for the integration of sensors and microsystems with CMOS electronics within a single package. Issueshowever such as solder wetting, void formation and controlling composition make formation of high-quality repeatable seals highly challenging. Towards this aim, this paper presents our experimental work characterizing the eutectic stack deposition. We detail our design methods and process flow, share our experiences in controlling electrochemical deposition of AuSnalloy and finally discuss usability of sequential electroplating process for the formation of hermetic eutectic bonds.

  • Conference paper
    Ahmadi N, Constandinou TG, Bouganis C, 2018,

    Spike rate estimation using Bayesian Adaptive Kernel Smoother (BAKS) and its application to brain machine interfaces

    , 40th International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Publisher: IEEE

    Brain Machine Interfaces (BMIs) mostly utilise spike rate as an input feature for decoding a desired motor output as it conveys a useful measure to the underlying neuronal activity. The spike rate is typically estimated by a using non-overlap binning method that yields a coarse estimate. There exist several methods that can produce a smooth estimate which could potentially improve the decoding performance. However, these methods are relatively computationally heavy for real-time BMIs. To address this issue, we propose a new method for estimating spike rate that is able to yield a smooth estimate and also amenable to real-time BMIs. The proposed method, referred to as Bayesian adaptive kernel smoother (BAKS), employs kernel smoothing technique that considers the bandwidth as a random variable with prior distribution which is adaptively updated through a Bayesian framework. With appropriate selection of prior distribution and kernel function, an analytical expression can be achieved for the kernel bandwidth. We apply BAKS and evaluate its impact on of fline BMI decoding performance using Kalman filter. The results show that overlap BAKS improved the decoding performance up to 3.33% and 12.93% compared to overlap and non-overlapbinning methods, respectively, depending on the window size. This suggests the feasibility and the potential use of BAKS method for real-time BMIs.

  • Journal article
    Liu Y, Pereira J, Constandinou TG, 2018,

    Event-driven processing for hardware-efficient neural spike sorting

    , Journal of Neural Engineering, Vol: 15, Pages: 1-14, ISSN: 1741-2552

    Objective. The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing. Approach. (1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability. Main results. It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources. Significance. By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.

  • Book chapter
    Williams I, Leene L, Constandinou TG, 2018,

    Next Generation Neural Interface Electronics

    , Circuit Design Considerations for Implantable Devices, Editors: Cong, Publisher: River Publishers, Pages: 141-178, ISBN: 978-87-93519-86-2
  • Patent
    Cavuto ML, Winter AG, Constandinou T, 2018,

    Apparatus and Method for Inserting Electrode-based Probes into Biological Tissue

  • Journal article
    Liu Y, Luan S, Williams I, Rapeaux A, Constandinou TGet al., 2017,

    A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput

    , IEEE Transactions on Biomedical Circuits and Systems, Vol: 11, Pages: 1344-1355, ISSN: 1932-4545

    Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.

  • Journal article
    Szostak K, Grand L, Constandinou TG, 2017,

    Neural interfaces for intracortical recording: requirements, fabrication methods, and characteristics

    , Frontiers in Neuroscience, Vol: 11, ISSN: 1662-4548

    Implantable neural interfaces for central nervous system research have been designed with wire, polymer or micromachining technologies over the past 70 years. Research on biocompatible materials, ideal probe shapes and insertion methods has resulted in building more and more capable neural interfaces. Although the trend is promising, the long-term reliability of such devices has not yet met the required criteria for chronic human application. The performance of neural interfaces in chronic settings often degrades due to foreign body response to the implant that is initiated by the surgical procedure, and related to the probe structure, and material properties used in fabricating the neural interface. In this review, we identify the key requirements for neural interfaces for intracortical recording, describe the three different types of probes- microwire, micromachined and polymer-based probes; their materials, fabrication methods, and discuss their characteristics and related challenges.

  • Conference paper
    Szostak K, Mazza F, Maslik M, Feng P, Leene L, Constandinou TGet al., 2017,

    Microwire-CMOS Integration of mm-Scale Neural Probes for Chronic Local Field Potential Recording

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 492-495
  • Conference paper
    Feng P, Constandinou TG, Yeon P, Ghovanloo Met al., 2017,

    Millimeter-Scale Integrated and Wirewound Coils for Powering Implantable Neural Microsystems

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 488-491
  • Conference paper
    De Marcellis A, Palange E, Faccio M, Stanchieri GDP, Constandinou TGet al., 2017,

    A 250Mbps 24pJ/bit UWB-inspired Optical Communication System for Bioimplants

    , Turin, Italy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 132-135
  • Conference paper
    Luo J, Firfilionis D, Ramezani R, Dehkhoda F, Soltan A, Degenaar P, Liu Y, Constandinou TGet al., 2017,

    Live demonstration: a closed-loop cortical brain implant for optogenetic curing epilepsy

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 169-169
  • Conference paper
    Mifsud A, Haci D, Ghoreishizadeh S, Liu Y, Constandinou TGet al., 2017,

    Adaptive Power Regulation and Data Delivery for Multi-Module Implants

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 584-587
  • Conference paper
    Leene L, Constandinou TG, 2017,

    A 0.5V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2619-2622, ISSN: 2379-447X

    This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nanometre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which isnot well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked ΔΣ behavior which is useful on-chip characterizationand interfacing with synchronous systems. A 0.5V instrumentation system is implemented using a 65nm TSMC technology to realize a highly compact footprint that is 0.006mm2 in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 Vrms input referred noise for the given 810nW total system power budget corresponding to an NEF of 1.64.

  • Journal article
    Ghoreishizadeh S, Haci D, Liu Y, Donaldson N, Constandinou TGet al., 2017,

    Four-Wire Interface ASIC for a Multi-Implant Link

    , IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Pages: 3056-3067, ISSN: 1549-8328

    This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical ‘optrodes’ that facilitate a bidirectional neural interface (electrical recording, optical stimulation), and chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate(up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) which is superimposed on a power carrier. On-chip power management provides an unregulated 5V DC supply with up to 2.5mA output current for stimulation, and two regulated voltages (3.3V and 3V) with 60 dB PSRR for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35 um CMOS technology, occupying 1.5mm2 silicon area,and consumes a quiescent current of 91.2u A. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.

  • Conference paper
    Troiani F, Nikolic K, Constandinou TG, 2017,

    Optical coherence tomography for compound action potential detection: a computational study

    , SPIE/OSA European Conferences on Biomedical Optics (ECBO), Pages: 1-3

    The feasibility of using time domain optical coherence tomography (TD-OCT)to detect compound action potential in a peripheral nerve and the setup characteristics, are studied through the use of finite-difference time-domain (FDTD) technique.

  • Journal article
    Leene L, Constandinou TG, 2017,

    Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

    , IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Pages: 3003-3012, ISSN: 1549-8328

    The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth- order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure- of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst addition- ally offering direct integration with digital systems.

  • Journal article
    Leene L, Constandinou TG, 2017,

    A 0.016² 12b ΔΣSAR With 14fJ/conv. for ultra low power biosensor arrays

    , IEEE Transactions on Circuits and Systems. Part 1: Regular Papers, Vol: 64, Pages: 2655-2665, ISSN: 1549-8328

    The instrumentation systems for implantable brain-machine interfaces represent one of the most demanding applications for ultra low-power analogue-to-digital-converters (ADC) to date. To address this challenge, this paper proposes a ΔΣSAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0-2 MASH topology. This configuration uses a specialized FIR window to decimate the ΔΣ modulator output and reject mismatch errors from the SAR quantizer, which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision. A fully differential prototype was fabricated using 0.18 μm CMOS to demonstrate 10.8 ENOB precision with a 0.016 mm² silicon footprint. Moreover, a 14 fJ/conv figure-of-merit can be achieved, while resolving signals with the maximum input amplitude of ±1.2,Vpp sampled at 200 kS/s. The ADC topology exhibits a number of promising characteristics for both high speed and ultra low-power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio, which are critical parameters for many sensor applications.

  • Conference paper
    Guven O, Eftekhar A, Kindt W, Constandinou TGet al., 2017,

    Low-power real-time ECG baseline wander removal: hardware implementation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1571-1574

    This paper presents a hardware realisation of a novel ECG baseline drift removal that preserves the ECG signal integrity. The microcontroller implementation detects the fiducial markers of the ECG signal and the baseline wander estimation is achieved through a weighted piecewise linear interpolation. This estimated drift is then removed to recover a “clean” ECG signal without significantly distorting the ST segment. Experimental results using real data from the MIT-BIH Arrhythmia Database (recording 100 and 101) with added baseline wander (BWM1) from the MIT-BIH Noise Stress Database show an average root mean square error of 34.3uV (mean), 30.4u V (median) and 18.4uV (standard deviation) per heart beat.

  • Conference paper
    Maslik M, Liu Y, Lande TS, Constandinou TGet al., 2017,

    A charge-based ultra-low power continuous-time ADC for data driven neural spike processing

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1420-1423

    The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75uW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4uW. The circuit has been implemented in a commercially available 0.35um CMOS technology with core occupying a footprint of 0.12 sq.mm

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