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  • Conference paper
    Gao C, Ghoreishizadeh S, Liu Y, Constandinou TGet al., 2017,

    On-chip ID generation for multi-node implantable devices using SA-PUF

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681

    This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 m CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.

  • Conference paper
    Haci D, Liu Y, Constandinou TG, 2017,

    32-channel ultra-low-noise arbitrary signal generation platform for biopotential emulation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701

    This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10kHz bandwidth, 110dB dynamic range and uV-level output noise.

  • Conference paper
    Dávila-Montero S, Barsakcioglu DY, Jackson A, Constandinou TG, Mason AJet al., 2017,

    Real-time clustering algorithm that adapts to dynamic changes in neural recordings

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 690-693

    This work presents a computationally efficient real-time adaptive clustering algorithm that recognizes and adapts to dynamic changes observed in neural recordings. The algorithm consists of an off-line training phase that determines initial cluster positions, and an on-line operation phase that continuously tracks drifts in clusters and periodically verifies acute changes in cluster composition. Analysis of chronic recordings from non-human primates shows that adaptive clustering achieves an improvement of 14% in classification accuracy and demonstrates an ability to recognize acute changes with 78% accuracy, with up to 29% computational efficiency compared to the state-of-the-art. The presented algorithm is suitable for long-term chronic monitoring of neural activity in various applications such as neuroscience research and control of neural prosthetics and assistive devices.

  • Conference paper
    Leene L, Constandinou TG, 2017,

    A 2.7uW/Mips, 0.88GOPS/mm^2 Distributed Processor for Implantable Brain Machine Interfaces

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 360-363

    This paper presents a scalable architecture in 0.18u m CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributedprocessor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7uW/MIPS with a total chip area of 1.37mm2. This configuration executes 1024 instructions on each core at 20MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.

  • Conference paper
    Frehlick Z, Williams I, Constandinou TG, 2017,

    Improving Neural Spike Sorting Performance Using Template Enhancement

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 524-527

    This paper presents a novel method for improving the performance of template matching in neural spike sorting for similar shaped spikes, without increasing computational complexity. Mean templates for similar shaped spikes are enhanced to emphasise distinguishing features. Template optimisation is based on the variance of sample distributions. Improved spike sorting performance is demonstrated on simulated neural recordings with two and three neuron spike shapes. The method is designed for implementation on a Next Generation Neural Interface (NGNI) device at Imperial College London.

  • Conference paper
    Luan S, Liu Y, Williams I, Constandinou TGet al., 2017,

    An Event-Driven SoC for Neural Recording

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 404-407

    This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs)and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Eachchannel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35u m CMOS technology occupying a silicon area of 19.1mm^2 (0.3mm^2 gross per channel) and requiring 32uW/channel power consumption (AFE only).

  • Conference paper
    Lauteslager T, Tommer M, Kjelgard KG, Lande TS, Constandinou TGet al., 2017,

    Intracranial Heart Rate Detection Using UWB Radar

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 119-122

    Microwave imaging is a promising technique for noninvasive imaging of brain activity. A multistatic array of body coupled antennas and single chip pulsed ultra-wideband radars should be capable of detecting local changes in cerebral blood volume, a known indicator for neural activity. As an initialverification that small changes in the cerebrovascular system can indeed be measured inside the skull, we recorded the heart rate intracranially using a single radar module and two body coupled antennas. The obtained heart rate was found to correspond to ECG measurements. To confirm that the measured signal was indeed from within the skull, we performed simulations to predict the time-of-flight of radar pulses passing through differentanatomical structures of the head. Simulated time-of-flight through the brain corresponded to the measured delay of heart rate modulation in the radar signal. The detection of intracranial heart rate using microwave techniques has not previously been reported, and serves as a first proof that functional neuroimaging using radar could lie within reach.

  • Conference paper
    Ghoreishizadeh S, Haci D, Liu Y, Constandinou Tet al., 2017,

    A 4-wire interface SoC for shared multi-implant power transfer and full-duplex communication

    , IEEE Latin American symposium on Circuits and Systems (LASCAS), Pages: 49-52

    This paper describes a novel system for recoveringpower and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. Thetarget application requires a singleChest Devicebe connectedto aBrain Implantconsisting of multiple identical optrodesthat record neural activity and provide closed loop opticalstimulation. The interface is integrated within each optrode SoCallowing full-duplex and fully-differential communication basedon Manchester encoding. The system features a head-to-chestuplink data rate (1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) superimposed on a power carrier.On-chip power management provides an unregulated 5 V DCsupply with up to 2.5 mA output current for stimulation, anda regulated 3.3 V with 60 dB PSRR for recording and logiccircuits. The circuit has been implemented in a 0.35μm CMOStechnology, occupying 1.4 mm2silicon area, and requiring a62.2μA average current consumption.

  • Journal article
    De Marcellis A, Palange E, Nubile L, Faccio M, Di Patrizio Stanchieri G, Constandinou Tet al., 2016,

    A pulsed coding technique based on optical UWB modulation for high data rate low power wireless implantable biotelemetry

    , Electronics, Vol: 5, Pages: 1-10, ISSN: 2079-9292

    This paper reports on a pulsed coding technique based on optical Ultra-wideband (UWB)modulation for wireless implantable biotelemetry systems allowing for high data rate link whilstenabling significant power reduction compared to the state-of-the-art. This optical data codingapproach is suitable for emerging biomedical applications like transcutaneous neural wirelesscommunication systems. The overall architecture implementing this optical modulation techniqueemploys sub-nanosecond pulsed laser as the data transmitter and small sensitive area photodiode asthe data receiver. Moreover, it includes coding and decoding digital systems, biasing and drivinganalogue circuits for laser pulse generation and photodiode signal conditioning. The complete systemhas been implemented on Field-Programmable Gate Array (FPGA) and prototype Printed CircuitBoard (PCB) with discrete off-the-shelf components. By inserting a diffuser between the transmitterand the receiver to emulate skin/tissue, the system is capable to achieve a 128 Mbps data rate with abit error rate less than 10 9 and an estimated total power consumption of about 5 mW correspondingto a power efficiency of 35.9 pJ/bit. These results could allow, for example, the transmission of an800-channel neural recording interface sampled at 16 kHz with 10-bit resolution.

  • Conference paper
    Lauteslager T, Nicolaou N, Lande TS, Constandinou TGet al., 2016,

    Functional neuroimaging Using UWB Impulse Radar: a Feasibility Study

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 406-409

    Microwave imaging is a promising new modalityfor studying brain function. In the current paper we assess thefeasibility of using a single chip implementation of an ultra-wideband impulse radar for developing a portable and low-costfunctional neuroimaging device. A numerical model is used topredict the level of attenuation that will occur when detectinga volume of blood in the cerebral cortex. A phantom liquid ismade, to study the radar’s performance at different attenuationlevels. Although the radar is currently capable of detecting apoint reflector in a phantom liquid with submillimeter accuracyand high temporal resolution, object detection at the desired levelof attenuation remains a challenge.

  • Conference paper
    Zhao H, Dehkhoda F, Ramezani R, Sokolov D, Constandinou TG, Liu Y, Degenaar Pet al., 2016,

    A CMOS-Based Neural Implantable Optrode for Optogenetic Stimulation and Electrical Recording

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 286-289

    This paper presents a novel integrated optrode for simultaneous optical stimulation and electrical recording for closed -loop optogenetic neuro-prosthetic applications. The design has been implemented in a commercially available 0.35μm CMOS process. The system includes circuits for controlling the optical stimulations; recording local field potentials (LFPs); and onboard diagnostics. The neural interface has two clusters of stimulation and recording sites. Each stimulation site has a bonding point for connecting a micro light emitting diode (μLED) to deliver light to the targeted area of brain tissue. Each recording site is designed to be post-processed with electrode materials to provide monitoring ofneural activity. On-chip diagnostic sensing has been included to provide real-time diagnostics for post-implantation and during normal operation.

  • Conference paper
    Ramezani R, Dehkhoda F, Soltan A, Degenaar P, Liu Y, Constandinou TGet al., 2016,

    An optrode with built-in self-diagnostic and fracture sensor for cortical brain stimulation

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 392-395

    This paper proposes a self-diagnostic subsystem for a new generation of brain implants with active electronics. The primary objective of such probes is to deliver optical pulses to optogenetic tissue and record the subsequent activity, but lifetime is currently unknown. Our proposed circuits aim to increase the safety of implanting active electronic probes into human brain tissue. Therefore, prolonging the lifetime of the implant and reducing the risks to the patient. The self-diagnostic circuit will examine the optical emitter against any abnormality or malfunctioning. The fracture sensor examinesthe optrode against any rapture or insertion breakage. The optrode including our diagnostic subsystem and fracture sensor has been designed and successfully simulated at 350nm AMS technology node and sent for manufacture.

  • Conference paper
    Williams I, Rapeaux A, Liu Y, Luan S, Constandinou TGet al., 2016,

    A 32-Channel Bidirectional Neural/EMG Interface with on-Chip Spike Detection for Sensorimotor Feedback

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 528-531

    This paper presents a novel 32-channel bidirectional neural interface, capable of high voltage stimulation and low power, low-noise neural recording. Current-controlled biphasic pulses are output with a voltage compliance of 9.25V, user configurable amplitude (max. 315 uA) & phase duration (max. 2 ms). The low-voltage recording amplifiers consume 23 uW per channel with programmable gain between 225 - 4725. Signals are10-bit sampled at 16 kHz. Data rates are reduced by granular control of active recording channels, spike detection and event-driven communication, and repeatable multi-pulse stimulation configurations.

  • Conference paper
    Luan S, Williams I, de Carvalho F, Jackson A, Quian Quiroga R, Constandinou TGet al., 2016,

    Next Generation Neural Interfaces for low-power multichannel spike sorting

    , FENS Forum of Neuroscience, Publisher: FENS
  • Conference paper
    Nicolaou N, Constandinou TG, 2016,

    Phase-Amplitude Coupling during propofol-induced sedation: an exploratory approach

    , FENS Forum of Neuroscience, Publisher: FENS
  • Conference paper
    De Marcellis A, Palange E, Faccio M, Nubile L, Di Patrizio Stanchieri G, Constandinou TGet al., 2016,

    A new optical UWB modulation technique for 250Mbps wireless link in implantable biotelemetry systems

    , Eurosensors, Publisher: Elsevier: Creative Commons Attribution Non-Commercial No-Derivatives License, ISSN: 1877-7058

    We propose a new UWB modulation technique for wireless optical communications in transcutaneous biotelemetry. The solution, based on the generation of sub-nanoseconds laser pulses, allows for a high data rate link whilst achieving a significant power reduction (energy per bit) compared to the state-ofthe- art. These features make this particularly suitable for emerging biomedical applications such as implantable neural/biosensor systems. The relatively simple architecture consists of a transmitter and receiver that can be integrated in a standard CMOS technology in a compact Silicon footprint (lower than 1mm^2 in a 0.18μm technology). These parts, optimised for low-voltage/low-power operation, include coding and decoding digital systems, biasing and driving analogue circuits for laser pulse generation and photodiode signal conditioning. Experimental findings with prototype PCBs have validated the new paradigm showing the system capabilities to achieve a BER less than 10^-9 with data rate up to 250Mbps and estimated total power consumption lower than 5mW.

  • Journal article
    Nicolaou N, Constandinou TG, 2016,

    A nonlinear causality estimator based on Non-Parametric Multiplicative Regression

    , Frontiers in Neuroinformatics, Vol: 10, ISSN: 1662-5196

    Causal prediction has become a popular tool for neuroscience applications, as it allows the study of relationships between different brain areas during rest, cognitive tasks or brain disorders. We propose a nonparametric approach for the estimation of nonlinear causal prediction for multivariate time series. In the proposed estimator, C-NPMR, Autoregressive modelling is replaced by Nonparametric Multiplicative Regression (NPMR). NPMR quantifies interactions between a response variable (effect) and a set of predictor variables (cause); here, we modified NPMR for model prediction. We also demonstrate how a particular measure, the sensitivity Q, could be used to reveal the structure of the underlying causal relationships. We apply C-NPMR on artificial data with known ground truth (5 datasets), as well as physiological data (2 datasets). C-NPMR correctly identifies both linear and nonlinear causal connections that are present in the artificial data, as well as physiologically relevant connectivity in the real data, and does not seem to be affected by filtering. The Sensitivity measure also provides useful information about the latent connectivity.The proposed estimator addresses many of the limitations of linear Granger causality and other nonlinear causality estimators. C-NPMR is compared with pairwise and conditional Granger causality (linear) and Kernel-Granger causality (nonlinear). The proposed estimator can be applied to pairwise or multivariate estimations without any modifications to the main method. Its nonpametric nature, its ability to capture nonlinear relationships and its robustness to filtering make it appealing for a number of applications.

  • Conference paper
    Barsakcioglu DY, Constandinou TG, 2016,

    A 32-Channel MCU-Based Feature Extraction and Classification for Scalable on-Node Spike Sorting

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1310-1313

    This paper describes a new hardware-efficientmethod and implementation for neural spike sorting basedon selection of a channel-specific near-optimal subset of fea-tures given a larger predefined set. For each channel, real-time classification is achieved using a simple decision matrixthat considers the features that provide the highest separabilitydetermined through off-line training. A 32-channel system for on-line feature extraction and classification has been implementedin an ARM Cortex-M0+ processor. Measured results of thehardware platform consumes 268 W per channel during spikesorting (includes detection). The proposed method provides atleast x10 reduction in computational requirements compared toliterature, while achieving an average classification error of lessthan 10% across wide range of datasets and noise levels.

  • Conference paper
    Elia M, Leene L, Constandinou TG, 2016,

    Continuous-Time Micropower Interface for Neural Recording Applications

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 534-637

    This paper presents a novel amplifier architectureintended for low power neural recording applications. By usingcontinuous-time signal representation, the proposed topologypredominantly leverages digital topologies taking advantage ofefficient techniques used in time domain systems. This includeshigher order feedback dynamics that allow direct analoguesignal quantization and near ideal integrator structures for noiseshaping. The system implemented in 0.18 μ m standard CMOSdemonstrates the capability for low noise instrumentation witha bandwidth of 6 kHz and highly linear full dynamic range.Simulation results indicate 1.145 μW budget from 0.5 V supplyvoltage with an input referred thermal noise of 7.7 μVrms.

  • Conference paper
    Liu Y, Pereira J, Constandinou TG, 2016,

    Clockless Continuous-Time Neural Spike Sorting: Method, Implementation and Evaluation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 538-541

    In this paper, we present a new method for neuralspike sorting based on Continuous Time (CT) signal processing.A set of CT based features are proposed and extracted fromCT sampled pulses, and a complete event-driven spike sortingalgorithm that performs classification based on these features isdeveloped. Compared to conventional methods for spike sorting,the hardware implementation of the proposed method does notrequire any synchronisation clock for logic circuits, and thusits power consumption depend solely on the spike activity. Thishas been implemented using a variable quantisation step CTanalogue to digital converter (ADC) with custom digital logicthat is driven by level crossing events. Simulation results usingsynthetic neural data shows a comparable accuracy comparedto template matching (TM) and Principle Components Analysis(PCA) based discrete sampled classification.

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