Imperial College London

MrAndreaMifsud

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Research Associate in Integrated Circuit Design
 
 
 
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Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

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11 results found

Maheshwari S, Stathopoulos S, Wang J, Serb A, Pan Y, Mifsud A, Leene LB, Shen J, Papavassiliou C, Constandinou TG, Prodromakis Tet al., 2021, Design flow for hybrid CMOS/memristor systems--Part II: circuit schematics and layout, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4876-4888, ISSN: 1549-8328

\normalsize The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

Journal article

Maheshwari S, Stathopoulos S, Wang J, Serb A, Pan Y, Mifsud A, Leene LB, Shen J, Papavassiliou C, Constandinou TG, Prodromakis Tet al., 2021, Design flow for hybrid CMOS/memristor systems--Part I: modeling and verification steps, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4862-4875, ISSN: 1549-8328

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

Journal article

Antoniadis DD, Feng P, Mifsud A, Constandinou TGet al., 2021, Open-source memory compiler for automatic RRAM generation and verification, 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Publisher: IEEE, Pages: 97-100

The lack of open-source memory compilers in academia typically causes significant delays in research and design implementations. This paper presents an open-source memory compiler that is directly integrated within the Cadence Virtuoso environment using physical verification tools provided by Mentor Graphics (Calibre). It facilitates the entire memory generation process from netlist generation to layout implementation, and physical implementation verification. To the best of our knowledge, this is the first open-source memory compiler that has been developed specifically to automate Resistive Random Access Memory (RRAM) generation. RRAM holds the promise of achieving high speed, high density and non-volatility. A novel RRAM architecture, additionally is proposed, and a number of generated RRAM arrays are evaluated to identify their worst case control line parasitics and worst case settling time across the memristors of their cells. The total capacitance of lines SEL, N and P is 5.83 fF/cell, 3.31 fF/cell and 2.48 fF/cell respectively, while the total calculated resistance for SEL is 1.28 Ω/cell and 0.14 Ω/cell for both N and P lines.

Conference paper

Haci D, Mifsud A, Liu Y, Ghoreishizadeh S, Constandinou Tet al., 2019, In-body wireline interfacing platform for multi-module implantable microsystems, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4

The recent evolution of implantable medical devicesfrom single-unit stimulators to modern implantable microsys-tems, has driven the need for distributed technologies, in whichboth the implant system and functions are partitioned across mul-tiple active devices. This multi-module approach is made possiblethanks to novel network architectures, allowing for in-body powerand data communications to be performed using implantableleads. This paper discusses the challenges in implementing suchinterfacing system and presents a platform based on one centralimplant (CI) and multiple peripheral implants (PIs) using a cus-tom 4WiCS communication protocol. This is implemented in PCBtechnology and tested to demonstrate intrabody communicationcapabilities and power transfer within the network. Measuredresults show CI-to-PI power delivery achieves 70%efficiency inexpected load condition, while establishing full-duplex data linkwith up to 4 PIs simultaneously.

Conference paper

Mifsud A, Sedgwick I, Guerrini N, 2019, Asynchronous sampling of an active non-synchronised time-to-digital converter, ELECTRONICS LETTERS, Vol: 55, Pages: 636-637, ISSN: 0013-5194

Journal article

Mifsud A, Haci D, Ghoreishizadeh SS, Liu Y, Constandinou TGet al., 2018, Adaptive power regulation and data delivery for multi-module implants, Pages: 1-4

Emerging applications for implantable devices are requiring multi-unit systems with intrabody transmission of power and data through wireline interfaces. This paper proposes a novel method for power delivery within such a configuration that makes use of closed loop dynamic regulation. This is implemented for an implantable application requiring a single master and multiple identical slave devices utilising a parallel-connected 4-wire interface. The power regulation is achieved within the master unit through closed loop monitoring of the current consumption to the wired link. Simultaneous power transfer and full-duplex data communication is achieved by superimposing the power carrier and downlink data over two wires and uplink data over a second pair of wires. Measured results using a fully isolated (AC coupled) 4-wire lead, demonstrate this implementation can transmit up to 120 mW of power at 6 V (at the slave device, after eliminating any losses). The master device has a maximum efficiency of 80 % including a dominant dynamic power loss. A 6 V constant supply at the slave device is recovered 1.5 ms after a step of 22 mA.

Conference paper

Mifsud A, 2017, Wired full-duplex communication and power delivery for medical implantable systems

Emerging applications for implantable devices require multi-node systems with intrabody transmission of power and data through wireline interfaces. Forming part of the CANDO project, this work provides the design and implementation of a PCB-based, master chest device. It focuses on achieving an efficient and AC-coupled system; providing an interface for power delivery and full-duplex data communication. Such an interface is used by a single master and multiple slave devices; utilising a parallel-connected 4-wire implantable cable. A novel adaptive power delivery method that makes use of closed loop dynamic regulation is being proposed. Regulation is attained within the master unit by closedloop monitoring of the current consumption owing through the wired link. Simultaneous power transfer and full-duplex data communication are achieved by superimposing the power carrier and downlink data over two wires, and the uplink data over a second pair of wires. Measured results using a fully isolated (AC coupled) 4-wire lead, demonstrate that this implementation can transmit up to 120mW of power at 6V (at the slave device, after eliminating any losses). The master device has a maximum system efficiency of 86 %, with a dominant dynamic power loss, and a maximum power transmission efficiency of 50 %. A 6V constant supply at the slave device is recovered 1.5 ms after a step of 22 mA. Downlink and uplink communication are achieved at a bit rate of 100 kbps and 1.6 Mbpsrespectively. The achieved bit error rate of the uplink is less than 1 %.

Thesis dissertation

Mifsud A, Shen J, Feng P, Xie L, Wang C, Pan Y, Maheshwari S, Agwa S, Stathopoulos S, Wang S, Serb A, Papavassiliou C, Prodromakis T, Constandinou TGet al., A CMOS-based Characterisation Platform for Emerging RRAM Technologies

Mass characterisation of emerging memory devices is an essential step inmodelling their behaviour for integration within a standard design flow forexisting integrated circuit designers. This work develops a novelcharacterisation platform for emerging resistive devices with a capacity of upto 1 million devices on-chip. Split into four independent sub-arrays, itcontains on-chip column-parallel DACs for fast voltage programming of the DUT.On-chip readout circuits with ADCs are also available for fast read operationscovering 5-decades of input current (20nA to 2mA). This allows a device'sresistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimumvoltage range of $\pm$1.5V on the device.

Journal article

Antoniadis D, Mifsud A, Feng P, Constandinou TGet al., An Open-Source RRAM Compiler

Memory compilers are necessary tools to boost the design procedure of digitalcircuits. However, only a few are available to academia. Resistive RandomAccess Memory (RRAM) is characterised by high density, high speed, nonvolatility and is a potential candidate of future digital memories. To the bestof the authors' knowledge, this paper presents the first open source RRAMcompiler for automatic memory generation including its peripheral circuits,verification and timing characterisation. The RRAM compiler is written withCadence SKILL programming language and is integrated in Cadence environment.The layout verification procedure takes place in Siemens Mentor Calibre tool.The technology used by the compiler is TSMC 180nm. This paper analyses thenovel results of a plethora of M x N RRAMs generated by the compiler, up to M =128, N = 64 and word size B = 16 bits, for clock frequency equal to 12.5 MHz.Finally, the compiler achieves density of up to 0.024 Mb/mm2.

Journal article

Shen J, Mifsud A, Xie L, Alshaya A, Papavassiliou Cet al., A High-Voltage Characterisation Platform For Emerging Resistive Switching Technologies

Emerging memristor-based array architectures have been effectively employedin non-volatile memories and neuromorphic computing systems due to theirdensity, scalability and capability of storing information. Nonetheless, todemonstrate a practical on-chip memristor-based system, it is essential to havethe ability to apply large programming voltage ranges during thecharacterisation procedures for various memristor technologies. This workpresents a 16x16 high voltage memristor characterisation array employing highvoltage CMOS circuitry. The proposed system has a maximum programming range of$\pm22V$ to allow on-chip electroforming and I-V sweep. In addition, a Kelvinvoltage sensing system is implemented to improve the readout accuracy for lowmemristance measurements. This work addresses the limitation of conventionalCMOS-memristor platforms which can only operate at low voltages, thus limitingthe characterisation range and integration options of memristor technologies.

Journal article

Xie L, Shen J, Mifsud A, Wang C, Alshaya A, Papavassiliou Cet al., A Wide Dynamic Range Read-out System For Resistive Switching Technology

The memristor, because of its controllability over a wide dynamic range ofresistance, has emerged as a promising device for data storage and analogcomputation. A major challenge is the accurate measurement of memristance overa wide dynamic range. In this paper, a novel read-out circuit with feedbackadjustment is proposed to measure and digitise input current in the rangebetween 20nA and 2mA. The magnitude of the input currents is estimated by a5-stage logarithmic current-to-voltage amplifier which scales a linearanalog-to-digital converter. This way the least significant bit tracks theabsolute input magnitude. This circuit is applicable to reading singlememristor conductance, and is also preferable in analog computing whereread-out accuracy is particularly critical. The circuits have been realized inBipolar-CMOS-DMOS (BCD) Gen2 technology.

Journal article

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