Publications
13 results found
Malik A, Mifsud A, Alshaya A, et al., 2023, The design of a resistive switching characterisation platform based on discrete current-conveyors, 2023 12th International Conference on Modern Circuits and Systems Technologies (MOCAST), Publisher: IEEE, Pages: 1-4
In this paper we propose a current-conveyor based circuit to characterise resistive switching devices. The circuit relies on open-loop current-mode techniques that are in principle faster than existing solutions that rely on transimpedance amplifiers for biasing and current sensing [1]. The circuit is able to apply a voltage across a test device and simultaneously provide a measure of current flowing through it. The circuit therefore, results in a compact solution that can be scaled-up to characterise crossbar devices in parallel. In this paper we describe, simulate and evaluate a discrete version of the proposed circuit. We also verify a PCB implementation that is capable of forming, writing and reading different types of resistive switching devices.
Shen J, Mifsud A, Xie L, et al., 2022, A high-voltage characterisation platform for emerging resistive switching technologies, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 3537-3541
Emerging memristor-based array architectures have been effectively employed in non-volatile memories and neuro-morphic computing systems due to their density, scalability and capability of storing information. Nonetheless, to demonstrate a practical on-chip memristor-based system, it is essential to have the ability to apply large programming voltage ranges during the characterisation procedures for various memristor technologies. This work presents a 16x16 high voltage memristor characterisation array employing high voltage CMOS circuitry. The proposed system has a maximum programming range of ±22V to allow on-chip electroforming and I-V sweep. In addition, a Kelvin voltage sensing system is implemented to improve the readout accuracy for low memristance measurements. This work addresses the limitation of conventional CMOS-memristor platforms which can only operate at low voltages, thus limiting the characterisation range and integration options of memristor technologies.
Xie L, Shen J, Mifsud A, et al., 2022, A wide dynamic range read-out system for resistive switching technology, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2003-2007
The memristor, because of its controllability over a wide dynamic range of resistance, has emerged as a promising device for data storage and analog computation. A major challenge is the accurate measurement of memristance over a wide dynamic range. In this paper, a novel read-out circuit with feedback adjustment is proposed to measure and digitise input current in the range between 20nA and 2mA. The magnitude of the input currents is estimated by a 5-stage logarithmic current-to-voltage amplifier which scales a linear analog-to-digital converter. This way the least significant bit tracks the absolute input magnitude. This circuit is applicable to reading single memristor conductance, and is also preferable in analog computing where read-out accuracy is particularly critical. The circuits have been realized in Bipolar-CMOS-DMOS (BCD) Gen2 technology.
Mifsud A, Shen J, Feng P, et al., 2022, A CMOS-based characterisation platform for emerging RRAM technologies, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 75-79
Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1kΩ and 10MΩ with a minimum voltage range of ±1.5V on the device.
Antoniadis D, Mifsud A, Feng P, et al., 2022, An Open-Source RRAM Compiler, 2022 20TH IEEE INTERREGIONAL NEWCAS CONFERENCE (NEWCAS), Pages: 465-469
Maheshwari S, Stathopoulos S, Wang J, et al., 2021, Design flow for hybrid CMOS/memristor systems--Part II: circuit schematics and layout, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4876-4888, ISSN: 1549-8328
\normalsize The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.
Maheshwari S, Stathopoulos S, Wang J, et al., 2021, Design flow for hybrid CMOS/memristor systems--Part I: modeling and verification steps, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4862-4875, ISSN: 1549-8328
Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.
Antoniadis DD, Feng P, Mifsud A, et al., 2021, Open-source memory compiler for automatic RRAM generation and verification, 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Publisher: IEEE, Pages: 97-100
The lack of open-source memory compilers in academia typically causes significant delays in research and design implementations. This paper presents an open-source memory compiler that is directly integrated within the Cadence Virtuoso environment using physical verification tools provided by Mentor Graphics (Calibre). It facilitates the entire memory generation process from netlist generation to layout implementation, and physical implementation verification. To the best of our knowledge, this is the first open-source memory compiler that has been developed specifically to automate Resistive Random Access Memory (RRAM) generation. RRAM holds the promise of achieving high speed, high density and non-volatility. A novel RRAM architecture, additionally is proposed, and a number of generated RRAM arrays are evaluated to identify their worst case control line parasitics and worst case settling time across the memristors of their cells. The total capacitance of lines SEL, N and P is 5.83 fF/cell, 3.31 fF/cell and 2.48 fF/cell respectively, while the total calculated resistance for SEL is 1.28 Ω/cell and 0.14 Ω/cell for both N and P lines.
Haci D, Mifsud A, Liu Y, et al., 2019, In-body wireline interfacing platform for multi-module implantable microsystems, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 1-4
The recent evolution of implantable medical devicesfrom single-unit stimulators to modern implantable microsys-tems, has driven the need for distributed technologies, in whichboth the implant system and functions are partitioned across mul-tiple active devices. This multi-module approach is made possiblethanks to novel network architectures, allowing for in-body powerand data communications to be performed using implantableleads. This paper discusses the challenges in implementing suchinterfacing system and presents a platform based on one centralimplant (CI) and multiple peripheral implants (PIs) using a cus-tom 4WiCS communication protocol. This is implemented in PCBtechnology and tested to demonstrate intrabody communicationcapabilities and power transfer within the network. Measuredresults show CI-to-PI power delivery achieves 70%efficiency inexpected load condition, while establishing full-duplex data linkwith up to 4 PIs simultaneously.
Mifsud A, Sedgwick I, Guerrini N, 2019, Asynchronous sampling of an active non-synchronised time-to-digital converter, ELECTRONICS LETTERS, Vol: 55, Pages: 636-637, ISSN: 0013-5194
Mifsud A, Sedgwick I, Guerrini N, 2019, time-to-digital conversion: A new architecture for time-to-digital converters from STFC researchers, Electronics Letters, Vol: 55, ISSN: 0013-5194
Mifsud A, Haci D, Ghoreishizadeh S, et al., 2017, Adaptive Power Regulation and Data Delivery for Multi-Module Implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 584-587
Mifsud A, 2017, Wired full-duplex communication and power delivery for medical implantable systems
Emerging applications for implantable devices require multi-node systems with intrabody transmission of power and data through wireline interfaces. Forming part of the CANDO project, this work provides the design and implementation of a PCB-based, master chest device. It focuses on achieving an efficient and AC-coupled system; providing an interface for power delivery and full-duplex data communication. Such an interface is used by a single master and multiple slave devices; utilising a parallel-connected 4-wire implantable cable. A novel adaptive power delivery method that makes use of closed loop dynamic regulation is being proposed. Regulation is attained within the master unit by closedloop monitoring of the current consumption owing through the wired link. Simultaneous power transfer and full-duplex data communication are achieved by superimposing the power carrier and downlink data over two wires, and the uplink data over a second pair of wires. Measured results using a fully isolated (AC coupled) 4-wire lead, demonstrate that this implementation can transmit up to 120mW of power at 6V (at the slave device, after eliminating any losses). The master device has a maximum system efficiency of 86 %, with a dominant dynamic power loss, and a maximum power transmission efficiency of 50 %. A 6V constant supply at the slave device is recovered 1.5 ms after a step of 22 mA. Downlink and uplink communication are achieved at a bit rate of 100 kbps and 1.6 Mbpsrespectively. The achieved bit error rate of the uplink is less than 1 %.
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