Publications
5 results found
Toupas P, Montgomerie-Corcoran A, Bouganis C-S, et al., 2023, HARFLOW3D: a latency-oriented 3D-CNN accelerator toolflow for HAR on FPGA devices, 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE Computer Society, Pages: 144-154, ISSN: 2576-2613
For Human Action Recognition tasks (HAR), 3D Convolutional Neural Networks have proven to be highly effective, achieving state-of-the-art results. This study introduces a novel streaming architecture-based toolflow for mapping such models onto FPGAs considering the model's inherent characteristics and the features of the targeted FPGA device. The HARFLOW3D toolflow takes as input a 3D CNN in ONNX format and a description of the FPGA characteristics, generating a design that minimises the latency of the computation. The toolflow is comprised of a number of parts, including (i) a 3D CNN parser, (ii) a performance and resource model, (iii) a scheduling algorithm for executing 3D models on the generated hardware, (iv) a resource-aware optimisation engine tailored for 3D models, (v) an automated mapping to synthesizable code for FPGAs. The ability of the toolflow to support a broad range of models and devices is shown through a number of experiments on various 3D CNN and FPGA system pairs. Furthermore, the toolflow has produced high-performing results for 3D CNN models that have not been mapped to FPGAs before, demonstrating the potential of FPGA-based systems in this space. Overall, HARFLOW3D has demonstrated its ability to deliver competitive latency compared to a range of state-of-the-art hand-tuned approaches, being able to achieve up to 5× better performance compared to some of the existing works. The tool is available at https://github.com/ptoupas/harflow3d.
Montgomerie-Corcoran A, Yu Z, Bouganis C-S, 2022, SAMO: optimised mapping of convolutional neural networks to streaming architectures, 32nd International Conference on Field-Programmable Logic and Applications (FPL), Publisher: IEEE, Pages: 418-424, ISSN: 1946-1488
Significant effort has been placed on the development of toolflows that map Convolutional Neural Network (CNN) models to Field Programmable Gate Arrays (FPGAs) with the aim of automating the production of high performance designs for a diverse set of applications. However, within these toolflows, the problem of finding an optimal mapping is often overlooked, with the expectation that the end user will tune their generated hardware for their desired platform. This is particularly prominent within Streaming Architecture toolflows, where there is a large design space to be explored. In this work, we establish the framework SAMO: a Streaming Architecture Mapping Optimiser. SAMO exploits the structure of CNN models and the common features that exist in Streaming Architectures, and casts the mapping optimisation problem under a unified methodology. Furthermore, SAMO explicitly explores the re-configurability property of FPGAs, allowing the methodology to overcome mapping limitations imposed by certain toolflows under resource-constrained scenarios, as well as improve on the achievable throughput. Three optimisation methods - Brute-Force, Simulated Annealing and Rule-Based - have been developed in order to generate valid, high performance designs for a range of target platforms and CNN models. Results show that SAMO-optimised designs can achieve 4x-20x better performance compared to existing hand-tuned designs. The SAMO framework is open-source: https://github.com/AlexMontgomerie/samo.
Montgomerie-Corcoran A, Bouganis C-S, 2021, POMMEL: Exploring Off-Chip Memory Energy & Power Consumption in Convolutional Neural Network Accelerators, 24th Euromicro Conference on Digital System Design (DSD), Publisher: IEEE COMPUTER SOC, Pages: 442-448
Montgomerie-Corcoran A, Savvas-Bouganis C, 2021, DEF: Differential Encoding of Featuremaps for Low Power Convolutional Neural Network Accelerators, 26th Asia and South Pacific Design Automation Conference (ASP-DAC), Publisher: IEEE, Pages: 703-708, ISSN: 2153-6961
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Montgomerie-Corcoran A, Venieris S, Bouganis C-S, 2019, Power-Aware FPGA Mapping of Convolutional Neural Networks, International Conference on Field-Programmable Technology (ICFPT), Publisher: IEEE COMPUTER SOC, Pages: 327-330
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- Citations: 4
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