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BibTex format

@article{Imtiaz:2017:10.1109/JSSC.2017.2647923,
author = {Imtiaz, SA and Jiang, Z and Rodriguez, Villegas E},
doi = {10.1109/JSSC.2017.2647923},
journal = {IEEE Journal of Solid State Circuits},
pages = {822--833},
title = {An ultra-low power system-on-chip for automatic sleep staging},
url = {http://dx.doi.org/10.1109/JSSC.2017.2647923},
volume = {52},
year = {2017}
}

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TY  - JOUR
AB  - This paper presents an ultra-low power SoC for automatic sleep staging using a single electroen-cephalography (EEG) channel. The system integrates an analog front-end for EEG data acquisition and adigital processor to extract spectral features from this data and classify them into one of the sleep stages.The digital processor consists of multiple blocks implementing an automatic sleep staging algorithmthat uses a set of contextual decision trees controlled by a state machine. The processor is designedto stay in idle mode at most times waking up only when computations are required. In addition, themathematical operations are implemented in a way such that the number of datapath components neededis very small. The SoC is implemented in AMS 0.18μm CMOS technology and is powered using asingle 1.25V supply. Its power consumption is measured to be575μW while its classification accuracyusing real EEG data is 98.7%.
AU  - Imtiaz,SA
AU  - Jiang,Z
AU  - Rodriguez,Villegas E
DO  - 10.1109/JSSC.2017.2647923
EP  - 833
PY  - 2017///
SN  - 1558-173X
SP  - 822
TI  - An ultra-low power system-on-chip for automatic sleep staging
T2  - IEEE Journal of Solid State Circuits
UR  - http://dx.doi.org/10.1109/JSSC.2017.2647923
UR  - http://hdl.handle.net/10044/1/43751
VL  - 52
ER  -

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Dr Syed Anas Imtiaz

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