Imperial College London

DrAzaleaRaad

Faculty of EngineeringDepartment of Computing

Senior Lecturer
 
 
 
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Contact

 

+44 (0)20 7594 8271azalea.raad Website

 
 
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Location

 

426Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Raad:2019:10.1145/3360561,
author = {Raad, A and Wickerson, J and Vafeiadis, V},
doi = {10.1145/3360561},
publisher = {Association for Computing Machinery (ACM)},
title = {Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models},
url = {http://dx.doi.org/10.1145/3360561},
year = {2019}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance of volatile memory (RAM). To describe the persistency guarantees of NVM, several memory persistency models have been proposed in the literature. However, the formal persistency semantics of mainstream hardware is unexplored to date. To close this gap, we present a formal declarative framework for describing concurrency models in the NVM context, and then develop the PARMv8 persistency model as an instance of our framework, formalising the persistency semantics of the ARMv8 architecture for the first time. To facilitate correct persistent programming, we study transactions as a simple abstraction for concurrency and persistency control. We thus develop the PSER (persistent serialisability) persistency model, formalising transactional semantics in the NVM context for the first time, and demonstrate that PSER correctly compiles to PARMv8. This then enables programmers to write correct, concurrent and persistent programs, without having to understand the low-level architecture-specific persistency semantics of the underlying hardware.
AU - Raad,A
AU - Wickerson,J
AU - Vafeiadis,V
DO - 10.1145/3360561
PB - Association for Computing Machinery (ACM)
PY - 2019///
SN - 2475-1421
TI - Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models
UR - http://dx.doi.org/10.1145/3360561
UR - http://hdl.handle.net/10044/1/74999
ER -